L9947 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

L9947

QUAD HALF-BRIDGE AND SINGLE HIGH-SIDE DRIVER

STMicroelectronics 

L9947

Bus Timing (figure 4)

The bus signal must be defined t3 = 1µs before

CSN goes low. It is allowed to change the level of

R/WN during CSN = 0. The other signals could be

changed. To store a command it is mandatory to

fix the D0 - D3 and MODE signals t9 = 1µs before

the positive edge of CSN.

OVERCURRENT AT OUT1 - OUT5:

The output currents of OUT1 - OUT5 are inter-

nally limited. This is realized in the following way:

When the output current reaches a certain level

(see pag...) the Gate - Source voltage will be

clamped to a lower level. The output current is

now limited and follows the output ID, UDS char-

acteristic for this Gate - Source voltage. An inter-

nal timer starts when the output voltage drop

(Drain - Source) increases above 0.4VS.

After 100µs typ. the output is switched OFF and

the corresponding overcurrent bit (OVC1 or

OVC2) will be set. The outputs can be activated

again with the next input data word.

Figure 4: Bus and Outputs Timing Diagram

lete Prodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss)) TIMING CHARACTERISTICS

bso Pro Symbol

O te t1

le t2

t3

sot4

Ob t5

Parameter

Width of CSN Low

Width of CSN High

Input Signals Before Negative Cdge of CSN

Input Signals After Positive Edge of CSN

Valid Diagnostic Data

Min. Typ. Max. Unit

20

90*

µs

10

µs

1

µs

1

µs

10

µs

t6

Valid Diagnostic Data

10

µs

t7

Delay Time from Input to Power Output, VS = 13V

300

µs

t8

CSN = Low Duration (Pulse Length) for CLEAR of latched Data

100

µs

t9

Input Data Before Positive Edge of CSN Which Should be Latched 1

µs

t1 and t5 are derived from the internal oscillator frequency

t7 varies with the supply voltage VS, relating to the output voltage slope limitation

(*) for t1 > 100µs the latched data will be reseted due to CLEAR (status 20)

9/13

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