HS-1212RH View Datasheet(PDF) - Intersil
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HS-1212RH Datasheet PDF : 9 Pages
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HS-1212RH
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH
PEAKING (dB)
BW (MHz)
±0.1dB GAIN FLATNESS (MHz)
Remove -IN Pin
4.5
430
21
+RS = 620Ω
+RS = 620Ω and Remove -IN Pin
Short +IN to -IN (e.g., Pins 2 and 3)
0
220
27
0.5
215
15
0.6
280
70
100pF Capacitor Between +IN and -IN
0.7
290
40
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Evaluation Board
The performance of the HS-1212RH may be evaluated using
the HA5023 Evaluation Board, slightly modified as follows:
1. Remove the two feedback resistors, and leave the
connections open.
2. a. For AV = +1 evaluation, remove the gain setting
resistors (R1), and leave pins 2 and 6 floating.
b. For AV = +2, replace the gain setting resistors (R1)
with 0Ω resistors to GND.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
To order evaluation boards (part number HA5023EVAL),
please contact your local sales office.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth
of 350MHz. By decreasing RS as CL increases (as
illustrated in the curves), the maximum bandwidth is
obtained without sacrificing stability. In spite of this,
bandwidth decreases as the load capacitance increases.
OUT
50Ω
1
R 1 (NOTE)
2
IN
3
50Ω
4
−5V
10µF
0.1µF
8
+5V
+−
7
6
0.1µF 10µF
5
GND
GND
NOTE: R1 = ∞ (AV = +1)
OR 0Ω (AV = +2)
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
50
40
30
20
AV = +1
AV = +2
10
0
0
50 100 150 200 250 300 350 400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
3
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