CXA1998AQ
Item
Low level
input voltage
High level
input voltage
Low level
output voltage
High level output
off leak current
Maximum clock
frequency
Minimum clock
pulse width
Minimum reset
pulse width
Minimum data
setup time
Minimum data
hold time
Minimum data
pulse width
Minimum latch
setup time
Minimum latch
hold time
Minimum clock
hold time
Measurement conditions
Min.
VIL (LATCH/CLK/DATA/XRESET)
(Pins 24, 25, 26, 27)
0.0
VIH (LATCH/CLK/DATA/XRESET)
(Pins 24, 25, 26, 27)
3.5
VOL, IOL = 2mA (max)
(Pins 15, 16, 17, 18, 19, 20, 21, 22)
0.0
IOZ Leak current which flows to the output
pin when IOZ output is open; applied
—
voltage is 10V. (Pins 15 to 22)
(1) fCK
500
(2) tWC
—
(3) tWR
—
(4) tSDK (DATA → CLK)
—
(5) tHCD (CLK → DATA)
—
(6) tWD
—
(7) tSLD (LATCH → DATA)
—
(8) tHCL (CLK → LATCH)
—
(9) tHLC (LATCH → CLK)
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max. Unit
1.5
VDD
V
0.5
1.0
µA
—
kHz
1.0
1.0
1.0
1.0
µs
2.0
1.0
1.0
1.0
Note)
• VDD is CPU supply voltage of 5.0V.
• VCC is 10.0V for high level output off-leak current.
• The threshold levels of low level input voltage and high level input voltage depend on VDD. Input level
detection is done by comparison with VDD/2. (Refer to “Equivalent circuit” of Pin Description.)
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