ADM1021AARQ View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADM1021AARQ Datasheet PDF : 16 Pages
| |||
ADM1021A
The ALERT interrupt latch is not reset by reading the Status
Register, but will be reset when the ALERT output has been
serviced by the master reading the device address, provided the
error condition has gone away and the Status Register flag bits
have been reset.
Configuration Register
Two bits of the configuration register are used. If Bit 6 is 0, which
is the power-on default, the device is in operating mode with the
ADC converting. If Bit 6 is set to 1, the device is in standby
mode and the ADC does not convert. Standby mode can also
be selected by taking the STBY pin low. In standby mode the val-
ues stored in the Remote and Local Temperature Registers remain
at the value they were when the part was placed in standby.
Bit 7 of the configuration register is used to mask the ALERT out-
put. If Bit 7 is 0, which is the power-on default, the ALERT output
is enabled. If Bit 7 is set to 1, the ALERT output is disabled.
Table IV. Configuration Register Bit Assignments
Power-On
Bit Name
Function
Default
7
MASK1
0 = ALERT Enabled 0
1 = ALERT Masked
6
RUN/STOP 0 = Run
0
1 = Standby
5–0
Reserved
0
Conversion Rate Register
The lowest three bits of this register are used to program the con-
version rate by dividing the ADC clock by 1, 2, 4, 8, 16, 32, 64,
or 128, to give conversion times from 125 ms (Code 07h) to 16
seconds (Code 00h). This register can be written to and read back
over the SMBus. The higher five bits of this register are unused
and must be set to zero. Use of slower conversion times greatly
reduces the device power consumption, as shown in Table V.
Table V. Conversion Rate Register Codes
Data
00h
01h
02h
03h
04h
05h
06h
07h
08h to FFh
Conversion/sec
0.0625
0.125
0.25
0.5
1
2
4
8
Reserved
Average Supply Current
µA Typ at VCC = 3.3 V
150
150
150
150
150
150
160
180
Limit Registers
The ADM1021A has four limit registers to store local and remote,
high and low temperature limits. These registers can be written
to and read back over the SMBus. The high limit registers
perform a > comparison while the low limit registers perform a
< comparison. For example, if the high limit register is pro-
grammed as a limit of 80°C, measuring 81°C will result in an
alarm condition. Even though the temperature measurement
range is from 0؇ to 127°C, it is possible to program the limit
register with negative values. This is for backwards-compatibility
with the ADM1021.
One-Shot Register
The one-shot register is used to initiate a single conversion and
comparison cycle when the ADM1021A is in standby mode,
after which the device returns to standby. This is not a data
register as such and it is the write operation that causes the one-
shot conversion. The data written to this address is irrelevant and
is not stored.
SERIAL BUS INTERFACE
Control of the ADM1021A is carried out via the serial bus. The
ADM1021A is connected to this bus as a slave device, under the
control of a master device. Note that the SMBus and SCL pins
are three-stated when the ADM1021A is powered down and will
not pull down the SMBus.
ADDRESS PINS
In general, every SMBus device has a 7-bit device address (except
for some devices that have extended, 10-bit addresses). When
the master device sends a device address over the bus, the slave
device with that address will respond. The ADM1021A has two
address pins, ADD0 and ADD1, to allow selection of the device
address, so that several ADM1021As can be used on the same
bus, and/or to avoid conflict with other devices. Although only
two address pins are provided, these are three-state, and can be
grounded, left unconnected, or tied to VDD, so that a total of
nine different addresses are possible, as shown in Table VI.
It should be noted that the state of the address pins is only sampled
at power-up, so changing them after power-up will have no effect.
Table VI. Device Addresses
ADD0
ADD1
Device Address
0
0
0
NC
0
1
NC
0
NC
NC
NC
1
1
0
1
NC
1
1
0011 000
0011 001
0011 010
0101 001
0101 010
0101 011
1001 100
1001 101
1001 110
ADD0, ADD1 sampled at power-up only.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDATA, while the serial clock line SCLK remains
high. This indicates that an address/data stream will follow.
All slave peripherals connected to the serial bus respond to
the START condition and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus an R/W bit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a 1, the master will read from the
slave device.
–8–
REV. D
Share Link: 