UT1553RTMP View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

UT1553RTMP

Remote Terminal Multi-Protocol

Aeroflex UTMC 

FUNCTIONAL DESCRIPTION

General Description

The RTMP is an interface device linking a MIL-STD-1553

serial data bus and a host microprocessor system (figure 2).

By selecting the correct state of the 1553 protocol select pin

(PRA/B = 1 for 1553A, 0 for 1553B), the system designer

can program the RTMP to comply fully with either MIL-

STD-1553A or MIL-STD-1553B.

The link between the 1553 data bus and the RTMP is the

shared memory area. All the data the RTMP transmits or

receives over the 1553 bus is stored in this shared memory

area. The RTMP accesses the shared memory with its DMA

signals (DMAR, DMAG, and DMAEN), the 16-bit

bidirectional data bus (D0-D15), and the 16-bit address bus

(A0-A15).

Since the RTMP’s architecture is based on a series of data

pointers, the 1553 transmit and receive data can be placed

anywhere in the 64K memory space, allowing the system

designer to optimize memory usage. The system designer

can program the RTMP to store the data received over the

1553 bus in one of two ways. The RTMP can store the

received data in a single data buffer or in separate buffers.

When the RTMP stores the received data in a single buffer,

all received data, regardless of subaddress, is stored in

contiguous locations in the shared memory. When the

RTMP stores the received data in separate buffers, the

RTMP stores the data associated with each of the 30

subaddresses in unique locations in memory.

The RTMP has six internal registers that provide the host

subsystem with RTMP control and status information.

Three of these registers are read/write: Time Tag Data

Register (TTD), the Control Register (CTL), and the Base

Pointer Data Register (BPD). Two are read only:

Operational Status Register (OPS), and the Last Command

Register (LCM). The Stop Self-Test Register (SST) is a

write-only register. To control the RTMP and the 1553

interface, the host begins by programming the Base Pointer

Data Register. By programming the BPD, the system

designer tells the RTMP where in the shared memory the

64-word Pointer Block will reside, whether the RTMP will

store the 1553 received data in single or separate buffers,

and how deep these data buffers will actually be. Figure 3

is a simple representation of the RTMP’s memory-mapping

architecture.

After the host has programmed the BPD, the 1553 interface

is enabled by setting either CHAEN or CHBEN in the

RTMP’s Control Register. The RTMP now monitors the

1553 data bus for a valid command word or mode code to

its particular terminal address. When received, the RTMP

looks at the mode bit (single/separate) in the BPD, the 1553

command transmit/receive bit, and the mode code or

subaddress portion of the 1553 command to determine

which of the address pointers in the 64-word Pointer Block

the RTMP will use for this particular memory transaction.

Each memory transaction consists of memory writes for

receive command words and memory reads for transmit

command words. This process continues until all 1553 data

words have been received or transmitted. If the host has

enabled any of the RTMP’s interrupts, the RTMP asserts

them when the memory transaction is complete.

RTMP-3

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