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G768B View Datasheet(PDF) - Global Mixed-mode Technology Inc

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G768B Datasheet PDF : 15 Pages
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Global Mixed-mode Technology Inc.
G768B
Ensuring a Valid Reset Output Down to VCC = 0V
When VCC falls below 1V, the G768B RESET output
no longer sinks current-it becomes an open circuit.
Therefore, high-impedance CMOS logic inputs con-
nected to RESET can drift to undetermined voltages.
This presents no problem in most applications, since
most µP and other circuitry is inoperative with VCC be-
low 1V. However, in applications where RESET must
be valid down to 0V, adding a pull-down resistor to
RESET causes any stray leakage currents to flow to
ground, holding RESET low (Figure 3). R1's value is
not critical; 100kis large enough not to load
RESET and small enough to pull RESET to ground.
Interfacing to Ps with Bi-directional Reset Pins
Ps with bi-directional reset pins (such as the Motorola
68HC11 series) can connect to the G768B reset out-
put. If, for example, the G768B RESET output is as-
serted high and the µP wants to pull it low, indetermi-
nate logic levels may result. To correct this, connect a
4.7kresistor between the G768B RESET output
and the µP reset I/O (Figure 4). Buffer the G768B
RESET output to other system components.
SMBus Digital Interface
From a software perspective, the G768B appears as a
set of byte-wide registers that contain temperature
data, alarm threshold values, fan speed data, or con-
trol bits, A standard SMBus 2-wire serial interface is
used to read temperature data and write control bits
and alarm threshold data. Each A/D and fan control
channel within the device responds to the same
SMBus slave address for normal reads and writes.
The G768B employs four standard SMBus protocols:
Write Byte, Read Byte, Send Byte, and Receive Byte
(Figure 5). The shorter Receive Byte protocol allows
quicker transfers, provided that the correct data regis-
ter was previously selected by a Read Byte instruction.
Use caution with the shorter protocols in multi-master
systems, since a second master could over-write the
command byte without informing the first master.
The temperature data format is 7bits plus sign in
twos-complement form for each channel, with each
data bit representing 1°C (Table3), transmitted MSB
first. Measurements are offset by +1/2°C to minimize
internal rounding errors; for example, +99.6°C is re-
ported as +100°C.
Benefits of Highly Accurate Reset Threshold
Most µP supervisor Ics have reset threshold voltages
between 5% and 10% below the value of nominal sup-
ply voltages. This ensures a reset will not occur within
5% of the nominal supply, but will occur when the sup-
ply is 10% below nominal.
When using Ics rated at only the nominal supply ±5%
this leaves a zone of uncertainty where the supply is
between 5% and 10% low, and where the reset may or
may not be asserted.
The G768B use highly accurate circuitry to ensure that
reset is asserted close to the 5% limit, and long before
the supply has declined to 10% below nominal.
BUFFER
VCC
G768B
4.7k
RESET
VCC
µP
RESET
BUFFERED RESET
TO OTHER SYSTEM
COMPONENTS
GND
GND
Fig 4. Interfacing to µPs with Bi-directional Reset I/O
VCC
G768B
RESET
GND
R1
100k
Fig 3. RESET Valid to VCC = Ground Circuit
Ver 1.3
Oct 28, 2002
TEL: 886-3-5788833
http://www.gmt.com.tw
9

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