AD724JR View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD724JR Datasheet PDF : 15 Pages
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AD724
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
1 STND
2 AGND
3 FIN
4 APOS
5 ENCD
6 RIN
7 GIN
8 BIN
9 CRMA
10 COMP
11 LUMA
12 SELECT
13 DGND
14 DPOS
15 VSYNC
16 HSYNC
A Logical HIGH input selects NTSC encoding.
A Logical LOW input selects PAL encoding.
CMOS/TTL Logic Levels.
Analog Ground Connection.
FSC clock or parallel-resonant crystal, or 4FSC clock input.
For NTSC: 3.579 545 MHz or 14.318 180 MHz.
For PAL: 4.433 619 MHz or 17.734 480 MHz.
CMOS/TTL Logic Levels for subcarrier clocks.
Analog Positive Supply (+5 V ± 5%).
A Logical HIGH input enables the encode function.
A Logical LOW input powers down chip when not in use.
CMOS/TTL Logic Levels.
Red Component Video Input.
0 to 714 mV AC-Coupled.
Green Component Video Input.
0 to 714 mV AC-Coupled.
Blue Component Video Input.
0 to 714 mV AC-Coupled.
Chrominance Output.*
Approximately 1.8 V peak-to-peak for both NTSC and PAL.
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NTSC and PAL.
Luminance plus SYNC Output.*
Approximately 2 V peak-to-peak for both NTSC and PAL.
A Logical LOW input selects the FSC operating mode.
A Logical HIGH input selects the 4FSC operating mode.
CMOS/TTL Logic Levels.
Digital Ground Connections.
Digital Positive Supply (+5 V ± 5%).
Vertical Sync Signal (if using external CSYNC set at > +2 V). CMOS/TTL Logic Levels.
Horizontal Sync Signal (or CSYNC signal). CMOS/TTL Logic Levels.
*The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75 Ω reverse-terminated lines.
Equivalent Circuit
Circuit A
Circuit B
Circuit A
Circuit C
Circuit C
Circuit C
Circuit D
Circuit D
Circuit D
Circuit A
Circuit A
Circuit A
DPOS
1
5
12
DGND
15
16
Circuit A
DPOS
DPOS
6
7
8
DGND
VCLAMP
Circuit C
APOS DPOS
3
DGND
VBIAS
Circuit B
Equivalent Circuits
9
10
11
AGND DGND
Circuit D
–4–
REV. B
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