CY7B993V-2ACT View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7B993V-2ACT Datasheet PDF : 15 Pages
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RoboClock
CY7B993V
CY7B994V
Absolute Maximum Conditions[5]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –40°C to + 125°C
Ambient Temperature with
Power Applied............................................ –40°C to + 125°C
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
DC Input Voltage....................................–0.3V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 40 mA
Static Discharge Voltage........................................... > 1100V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................. > ± 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 10%
3.3V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max. Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min., IOH = –30 mA 2.4
LOCK
IOH = –2 mA, VCC = Min.
2.4
VOL
LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min., IOL= 30 mA
–
LOCK
IOL= 2 mA, VCC = Min.
–
IOZ
High-impedance State Leakage Current
–100
LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])
–
V
–
V
0.5
V
0.5
V
100 µA
VIH
LVTTL Input HIGH FBK[A:B]±, REF[A:B]±
Min. < VCC < Max.
REFSEL, FBSEL, FBDIS,
DIS[1:4]
2.0 VCC + 0.3 V
2.0 VCC + 0.3 V
VIL
LVTTL Input LOW FBK[A:B]±, REF[A:B]±
Min. < VCC < Max.
–0.3
0.8
V
REFSEL, FBSEL, FBDIS, DIS[1:4]
–0.3
0.8
V
II
LVTTL VIN >VCC
FBK[A:B]±, REF[A:B]±
VCC = GND, VIN = 3.63V
–
100 µA
IlH
LVTTL Input HIGH FBK[A:B]±, REF[A:B]±
VCC = Max., VIN = VCC
–
500 µA
Current
REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VCC
–
500 µA
IlL
LVTTL Input LOW FBK[A:B]±, REF[A:B]±
VCC = Max., VIN = GND –500
–
µA
Current
REFSEL, FBSEL, FBDIS, DIS[1:4]
–500
–
µA
Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))
VIHH
VIMM
VILL
Three-level Input HIGH[6]
Three-level Input MID[6]
Three-level Input LOW[6]
Min. < VCC < Max.
Min. < VCC < Max.
Min. < VCC < Max.
0.87*VCC –
V
0.47*VCC 0.53*VCC V
– 0.13*VCC V
IIHH
Three-level Input Three-level input pins excl. FBF0 VIN = VCC
HIGH Current
FBF0
–
200 µA
–
400 µA
IIMM
Three-level Input Three-level input pins excl. FBF0 VIN = VCC/2
MID Current
FBF0
–50
–100
50
µA
100 µA
IILL
Three-level Input Three-level input pins excl. FBF0 VIN = GND
LOW Current
FBF0
–200
–400
–
µA
–
µA
LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)
VDIFF
Input Differential Voltage
400
VCC
mV
VIHHP
Highest Input HIGH Voltage
1.0
VCC
V
VILLP
Lowest Input LOW Voltage
GND VCC – 0.4 V
VCOM
Common Mode Range (crossing voltage)
0.8
VCC
V
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
Document #: 38-07127 Rev. *F
Page 8 of 15
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