SCANPSC110FSC View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
SCANPSC110FSC
Fairchild Semiconductor
SCANPSC110FSC Datasheet PDF : 25 Pages
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Level 1 Protocol (Continued)
FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register
FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register
Level 2 Protocol
Once the SCANPSC110F Bridge has been successfully
addressed and selected, its internal registers may be
accessed via Level-2 Protocol. Level-2 Protocol is compli-
ant to IEEE Std. 1149.1 TAP protocol with one exception: if
the SCANPSC110F is selected via the Broadcast or Multi-
Cast address, TDOB will always be 3-STATED. (The TDOB
buffer must be implemented this way to prevent bus con-
tention.)
Upon being selected, (i.e., the SCANPSC110F Selection
controller transitions from the Wait-For-Address state to
one of the Selected states), each of the local scan ports
(LSP1, LSP2, LSP3) remains parked in one of the following
four TAP Controller states: Test-Logic-Reset, Run-Test/
Idle, Pause-DR, or Pause-IR and the active scan chain will
consist of: TDIB through the instruction register (or the
IDCODE register) and out through TDOB.
TDIB→Instruction Register→TDOB
The UNPARK instruction (described later) is used to insert
one or more local scan ports into the active scan chain.
Table 4 describes which local ports are inserted into the
chain, and in what order.
LEVEL 2 INSTRUCTION TYPES
There are two types of instructions (reference Table 5):
1. Instructions that insert a SCANPSC110F register into
the active scan chain so that the register can be cap-
tured or updated (BYPASS, SAMPLE/PRELOAD,
EXTEST, IDCODE, MODESEL, MCGRSEL, LFSR-
SEL, CNTRSEL).
2. Instructions that configure local ports or control the
operation of the linear feedback shift register and
counter registers (UNPARK, PARKTRL, PARKRTI,
PARKPAUSE, GOTOWAIT, SOFTRESET, LFSRON,
LFSROFF, CNTRON, CNTROFF). These instructions,
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