SCANPSC110FSC View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

Manufacturer

SCANPSC110FSC

SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)

Fairchild Semiconductor 

Overview of SCANPSC110F Bridge Functions (Continued)

FIGURE 5. Relationship Between SCANPSC110F Bridge State Machines

Following a hardware reset, the TAP controller state-

machine is in the Test-Logic-Reset (TLR) state; the

SCANPSC110F-selection state-machine is in the Wait-For-

Address state; and each of the three port-selection state-

machines is in the Parked-TLR state. The SCANPSC110F

is then ready to receive Level-1 protocol, followed by Level-

2 protocol.

Tester/SCANPSC110F

Bridge Interface

An IEEE 1149.1 system tester sends instructions to a

SCANPSC110F via that SCANPSC110F’s backplane scan-

port. Following test logic reset, the SCANPSC110F’s selec-

tion state-machine is in the Wait-For-Address state. When

the SCANPSC110F’s TAP controller is sequenced to the

Shift-IR state, data shifted in through the TDIB input is

shifted into the SCANPSC110F’s instruction register. Note

that prior to successful selection of a SCANPSC110F, data

is not shifted out of the instruction register and out through

the SCANPSC110F’s TDOBoutput, as it is during normal

scan operations. Instead, as each new bit enters the

instruction register’s most-significant bit, data shifted out

from the least-significant bit is discarded.

When the instruction register is updated with the address

data, the SCANPSC110F’s address-recognition logic com-

pares the six least-significant bits of the instruction register

with the 6-bit assigned address which is statically present

on the S(0–5) inputs. Simultaneously, the scanned-in

address is compared with the reserved Broadcast and

Multi-cast addresses. If an address match is detected, the

SCANPSC110F-selection state-machine enters one of the

two selected states. If the scanned address does not match

a valid single-slot address or one of the reserved broad-

cast/multi-cast addresses, the SCANPSC110F-selection

state-machine enters the Unselected state.

Note that the SLOT inputs should not be set to a value cor-

responding to a multi-cast group, or to the broadcast

address. Also note that the single-SCANPSC110F selec-

tion process must be performed for all SCANPSC110Fs

which are subsequently to be addressed in multi-cast

mode. This is required because each such device’s Multi-

cast Group Register (MCGR) must be programmed with a

multi-cast group number, and the MCGR is not accessible

to the test controller until that SCANPSC110F has first

entered the Selected-Single-SCANPSC110F state.

Once a SCANPSC110F has been selected, Level-2 proto-

col is used to issue commands and to access the chip’s

various registers.

7

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