CY7C1350 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1350 Datasheet PDF : 13 Pages
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PRELIMINARY
Switching Waveforms
READ/WRITE/DESELECT Sequence
CY7C1350
CLK
CEN
tCH tCL
tAS tAH
ADDRESS RA1
WA2
RA3
tCYC
tCENS
RA4
WA5
RA6
RA7
tCENH
CEN HIGH blocks
all synchronous inputs
WE &
BWS[3:0]
tWS tWH
tCES tCEH
CE
Data-
In/Out
tCLZ
Device
originally
deselected
tDOH
Q1
Out
tCO
tDS tDH
D2
In
tCHZ
Q3
Out
tDOH
Q4
D5
Out
In
tCHZ
Q6
Q7
Out
Out
The combination of WE & BWS[3:0] define a write cycle (see write cycle definition table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
OE held LOW.
= DON’T CARE
= UNDEFINED
10
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