CY7C1350 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1350 Datasheet PDF : 13 Pages
| |||
fax id: 1103
PRELIMINARY
CY7C1350
128Kx36 Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
• Pin compatible and functionally equivalent to ZBT™ de-
vices IDT71V546, MT55L128L36P and MCM63Z736
• Supports 143-MHz bus operations with zero wait
states—Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined op-
eration
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast Clock-to-output times
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP package
• Burst Capability — linear or interleaved burst order
• Low standby power
Logic Block Diagram
CLK
ADV/LD
A[16:0] 17
CEN
CE1
CE2
CE3
WE
CONTROL
and WRITE
LOGIC
17
BWS[3:0]
MODE
The CY7C1350 is a 3.3V 128K by 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350 is equipped with the advanced No
Bus Latency (NoBL™) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Write/Read transitions. The CY7C1350 is pin/functionally
compatible to ZBT™ SRAMs IDT71V546, MT55L128L36P and
MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
4.0 ns (143-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS[3:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank selec-
tion and output three-state control. In order to avoid bus con-
tention, the output drivers are synchronously three-stated dur-
ing the data portion of a write sequence.
CE
DaDta-In
Q
REG.
36
36
128Kx36
36
MEMORY
ARRAY
36
DQ[31:0]
DP[3:0]
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
.
Commercial
Commercial
7C1350-143
4.0
TBD
TBD
7C1350-133
4.2
TBD
TBD
7C1350-100
5.0
TBD
TBD
7C1350-80
7.0
TBD
TBD
NoBL is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 4, 1998-Revised April 1998
Share Link: 