CY7C1350 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1350 Datasheet PDF : 13 Pages
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PRELIMINARY
CY7C1350
Switching Characteristics Over the Operating Range[10]
-143
-133
-100
-80
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
Clock Cycle Time
7.0
7.5
10
12.5
ns
tCH
Clock HIGH
2.0
3.0
4.0
4.0
ns
tCL
Clock LOW
2.0
3.0
4.0
4.0
ns
tAS
Address Set-Up Before CLK Rise
2.0
2.0
2.2
2.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
1.0
ns
tCO
Data Output Valid After CLK Rise
4.0
4.2
5.0
7.0 ns
tDOH
Data Output Hold After CLK Rise
1.5
1.5
1.5
1.5
ns
tCENS
CEN Set-Up Before CLK Rise
2.0
2.0
2.2
2.5
ns
tCENH
CEN Hold After CLK Rise
0.5
0.5
0.5
1.0
ns
tWES
GW, BWS[3:0] Set-Up Before CLK Rise
2.0
2.0
2.2
2.5
ns
tWEH
GW, BWS[3:0] Hold After CLK Rise
0.5
0.5
0.5
1.0
ns
tALS
ADV/LD Set-Up Before CLK Rise
2.0
2.0
2.2
2.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
1.0
ns
tDS
Data Input Set-Up Before CLK Rise
1.7
1.7
2.0
2.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
1.0
ns
tCES
Chip Enable Set-Up Before CLK Rise
2.0
2.0
2.2
2.5
ns
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
tEOV
Chip Enable Hold After CLK Rise
Clock to High-Z[11,12,13,14]
Clock to Low-Z[11,12,13,14]
OE HIGH to Output High-Z[11,12,13,14]
OE LOW to Output Low-Z[11,12,13,14]
OE LOW to Output Valid[13]
0.5
0.5
0.5
1.0
ns
1.5 3.5 1.5 3.5 1.5 3.5 1.5 5.0 ns
2.0
2.0
2.0
2.0
ns
4.0
4.2
5.0
7.0 ns
0
0
0
0
ns
4.0
4.2
5.0
7.0 ns
Notes:
10. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in
part (a) of AC Test Loads.
11. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
12. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. Tested initially and after any design or process change that may affect these parameters.
14. This parameter is sampled and not 100% tested.
9
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