CXD3504R View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
Manufacturer
CXD3504R Datasheet PDF : 12 Pages
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CXD3504R
Electrical Characteristics
(Input/Output level/VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C)
Item
Symbol Conditions
Min.
Typ. Max. Unit Applicable pins
High level input voltage VIH
Low level input voltage VIL
CMOS input
0.7VDD
—
—
V
∗1, ∗2, ∗3
—
—
0.2VDD V
High level output voltage VOH
Low level output voltage VOL
IOH = –12mA
IOL = 12mA
VDD – 0.8 —
—
—
—
V
∗4
0.4
V
Input leak current
IIL
VI = VSS, VDD
–10
—
10
µA ∗1, ∗2, ∗3
Pull-up resistor
RUP
80
160
320
kΩ ∗2
Pull-down resistor
RDN
90
180
360
kΩ ∗3
∗1 Input pins except PECLCK
∗2 XCLR
∗3 CLKSEL, SELRA, SELGA, SELBA, SELB, HDSEL, HDEDGE, REDGE, GEDGE, BEDGE, POLSLA
∗4 All output pins
AC Characteristics
PECLCK
(CMOSCK)
HD
Input Data
(R, G, B )
Through
Output
Delay
Output
t1
t2
t3
t4
d in d in d in d in d in d in d in d in d in
99b 100b 1c
2c
3c
4c
5c
6c
7c
, din din din din din din
95b 96b 97b 98b 99b 100b
No Care
, din din din din din din
95a 96a 97a 98a 99a 100a
No Care
d in d in d in d in d in d in
8c
9c 10c 11c 12c 13c
t5
d in d in d in d in d in d in
4c
5c
6c
7c
8c
9c
d in d in d in d in d in d in
4b 5b 6b 7b 8b 9b
Item
Symbol Min. Max. Unit
Input frequency
f
—
80 MHz
HD set-up time to PECLCK bar
HD hold time from PECLCK bar
t1
1.5
—
ns
t2
4.5
—
ns
R, G, B input data set-up time to PECLCK bar t3
R, G, B input data hold time from PECLCK bar t4
1
—
ns
6.5
—
ns
R, G, B output data delay from PECLCK
t5
HD set-up time to CMOSCK bar
t1
4
13
ns
2
—
ns
HD hold time from CMOSCK bar
t2
R, G, B input data set-up time to CMOSCK bar t3
3
—
ns
1.5
—
ns
R, G, B input data hold time from CMOSCK bar t4
R, G, B output data delay from CMOSCK
t5
4.5
—
ns
3
12
ns
Note: The above timing values are for PECCLK (CMOSCK) = 80MHz and an output pin capacitance of 20pF.
–9–
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