GS880F18T View Datasheet(PDF) - Giga Semiconductor
Part Name
Description
Manufacturer
GS880F18T Datasheet PDF : 25 Pages
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Preliminary
GS880F18/36T-10/11/11.5/12/14
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
VDDQ
VCK
VI/O
VIN
IIN
IOUT
PD
TSTG
TBIAS
Voltage on VDD Pins
-0.5 to 4.6
V
Voltage in VDDQ Pins
-0.5 to VDD
V
Voltage on Clock Input Pin
-0.5 to 6
V
Voltage on I/O Pins
-0.5 to VDDQ+0.5 (≤ 4.6 V
max.)
V
Voltage on Other Input Pins
-0.5 to VDD+0.5 (≤ 4.6 V max.)
V
Input Current on Any Pin
+/- 20
mA
Output Current on Any I/O Pin
+/- 20
mA
Package Power Dissipation
1.5
W
Storage Temperature
-55 to 125
oC
Temperature Under Bias
-55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol Min.
Typ.
Max.
Unit
Notes
Supply Voltage
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
2.5
VDD
V
1
Input High Voltage
VIH
1.7
---
VDD+0.3
V
2
Input Low Voltage
VIL
-0.3
---
0.8
V
2
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
3
Ambient Temperature (Industrial Range Versions)
TA
-40
25
85
°C
3
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC.
Rev: 1.03 3/2000
11/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
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