VES1820X View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

VES1820X

Single chip DVB-C channel receiver

Philips Electronics 

Philips Semiconductors

Single chip DVB-C channel receiver

FIGURE 6 : PARALLEL OUTPUT INTERFACE MODE A

OCLK

DO(7:0)

47H D1

D2

DEN

D187

PSYNC

UNCOR

Product specification

VES1820X

47H

Notes :

- OCLK is a jittered clock which average frequency is N*SymbolRate/8, where N is the spectral

efficiency of the modulation. The polarity of OCLK is programmable.

- DEN is active high (if PDEN=0) only during the 188 bytes of a packet

- PSYNC is active high (if PPSYNC=0) only during the sync byte (47H)

FIGURE 7 : PARALLEL OUTPUT INTERFACE MODE B

OCLK

DO(7:0)

47H D1

D2

D187

47H

DEN

PSYNC

UNCOR

Notes :

- OCLK is a division of the sampling clock by a programmable factor from 1 to 16. So it is a regular

clock which frequency must be greater than N*SymbolRate/8, where N is the spectral efficiency of

the modulation. The polarity of OCLK is programmable.

- DEN is active high (if PDEN=0) only during the valid bytes

- PSYNC is active high (if PPSYNC=0) only during the sync byte (47H)

1999 March 01

13

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