CA3194 View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
CA3194 Datasheet PDF : 9 Pages
| |||
Specifications CA3194
Electrical Specifications TA = +25oC, VCC = 12V, VS = 2.85V, VC = 2.85V, VAB = VPB = VCC, VB adjusted for V18 = 6.3V, CX adjusted
for FOSC = 4.43361875MHz, Sandcastle: VBG = 8.0V, VBLANK = 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit (Continued)
PARAMETER
TEST CONDITIONS
Saturation Control Range (Terminal 3)
For control characteristic, see Figure 10.
Maximum Chroma Output Voltage (Terminal 2) Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P.
Adjust VC and VS for maximum Pin 2 output.
OSCILLATOR SECTION
Pull-In Range
Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P.
Adjust CX for HI/LO fOSC without Chroma signal.
Apply signal to lock.
Static Phase Error
TYPICAL
VALUE
0-5
2.5
±500
2
DEMODULATOR SECTION
R-Y Demodulator Conversion Gain
Chroma Input: Burst =100mV, Chroma = 220mVP-P,Vø.
10
Adjust VC for V18 = 1V. Read V15. Calculate V18/V15.
B-Y Demodulator Conversion Gain
Chroma Input: Burst = 100mVP-P, Uø. Read V16 and V14.
18
Calculate V16/V14. VC remains as for R-Y gain.
G-Y/B-Y Matrix Ratio
Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Uø
0.2
read V17 and V16, Calculate V17/V16. VC remains as above.
G-Y/R-Y Matrix Ratio
Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Vø.
0.5
Read V17 and V18. Calculate V17/V18. VC remains as above.
Sub-Carrier and Harmonic Content at Outputs No Chroma or Luma Input. Read residual carrier at outputs.
30
SANDCASTLE PULSE
Horizontal and Vertical Blanking Pedestal
2-5
Burst Gate Pulse
NOTES:
1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17.
2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals.
3. The reference voltage can be adjusted by changing the values of the voltage divider.
6.5 - VCC
UNITS
VDC
VP-P
Hz
Deg./
100Hz
Ratio
Ratio
Ratio
Ratio
mVP-P
V
V
Circuit Description (See Block Diagram and Figure 20)
The chroma signal is externally separated from the video
signal by means of a bandpass or high-pass filter and
applied to pin 4. The burst is separated in the first chroma
stage and applied to the synchronous detector which pro-
vides information to sample-and-hold circuits for APC
(phase-locked loop), ACC (automatic chroma gain control)
and identification and killing. The 4.43MHz crystal oscillator
is phase-locked to the burst and provides 0 degrees and 90
degrees (via an external phase shifter) carriers to the
chroma demodulators. The burst and chroma amplitude at
the output of the first chroma amplifier is kept constant by
the automatic gain control.
A buffer stage drives the external PAL delay line. The sepa-
rated U and V signals are applied to pins 14 and 15, respec-
tively, and demodulated. A standard G-Y matrix is included
on the chip.
The luminance signal passes through the subcarrier trap
and through the luminance delay line and enters the chip at
pin 20. Contrast and brightness control is provided before
the luminance signal is combined with the color difference
signals in the Y matrix. Average and peak beam limiting cir-
cuits are controlled from pins 24 and 19.
The second chroma stage provides saturation control (pin 3)
which tracks the contrast control in the luminance channel.
This stage is also used for color killing.
7-58
Share Link: 