L6256 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

L6256

12V COMBO

STMicroelectronics 

Read and write clock rates may differ by as much

as 2:1. Clock rates may differ between different

chips using the bus.

A logic inversion may be used by other chips on

the bus. If this is done, use of the chip select line

after transmissions to the other chips is manda-

tory.

Chip Select

The external chip select masks out any incoming

data. When inactive, the serial port bit clocking

state machine is cleared, providing a resync

mechanism. The chip select may not change

states between every packet transmission, so it

should not be counted on as a continuous signal.

If the Dolphin is the only chip on the serial port,

the chip select will only be used an emergency re-

sync if the chip doesn’t answer queries.

Figure 5. Serial Port Chip Select Operation.

L6256

If an address byte is received that is not ad-

dressed to the Dolphin while chip select is active,

the Dolphin will ignore the transmission.

A metal option in the chip select circuit will allow

for either polarity of active level. Present intention

is for an active high level on the chip select pin.

Logic Inversion on Serial Port

If a logic inversion is used by other chips on the

serial bus, the R/W bit will assume the wrong

state and the Dolphin state mechanism will lose

synchronization. In this situation, it will be manda-

tory for the processor to deassert the chip select

to mask the serial port data intended for the other

chip.

Typical bus waveforms are shown below, with the

resultant activity.

1) Block Mode Write - To other chip

A1

D

SCLK

SDIO

wrong

address

CSELB

(A1 and A2 ignored)

2) Valid Writes to L6256

A1

D

SCLK

SDIO

CSELB

B

(All Data Written)

A2

D

A2

D

D97IN588

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