AD7667 View Datasheet(PDF) - Analog Devices
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AD7667 Datasheet PDF : 28 Pages
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AD7667
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Symbol Min
Typ
Max
Unit
Refer to Figure 33 and Figure 34
Convert Pulse Width
t1
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1
t2
CNVST LOW to BUSY HIGH Delay
t3
BUSY HIGH All Modes except Master Serial Read after Convert
t4
Aperture Delay
t5
End of Conversion to BUSY LOW Delay
t6
Conversion Time
t7
Acquisition Time
t8
RESET Pulse Width
t9
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
10
1/1.25/1.5
2
10
250
10
ns
µs
35
ns
0.75/1/1.25 µs
ns
ns
0.75/1/1.25 µs
ns
ns
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)2
t10
t11
12
t12
t13
5
0.75/1/1.25 µs
ns
45
ns
15
ns
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay2
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period3
Internal SCLK HIGH3
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SCLK Last Edge to SYNC Delay3
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)2
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t14
10
ns
t15
10
ns
t16
10
ns
t17
25/275/525
ns
t18
3
ns
t19
25
40
ns
t20
12
ns
t21
7
ns
t22
4
ns
t23
2
ns
t24
3
ns
t25
10
ns
t26
10
ns
t27
10
ns
t28
See Table 4
t29
0.75/1/1.25
µs
t30
25
ns
t31
5
t32
3
t33
5
t34
5
t35
25
t36
10
t37
10
ns
18
ns
ns
ns
ns
ns
ns
1In Warp mode only, the time between conversions is 1ms; otherwise there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In Serial Master Read During Convert mode. See Table 4 for Serial Master Read After Convert Mode.
Rev. 0 | Page 5 of 28
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