VSC6511 View Datasheet(PDF) - Vitesse Semiconductor
Part Name
Description
Manufacturer
VSC6511 Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
SMPTE 292M Serializer, Deserializer, and
Deserializer/Reclocker
Advance Product Information
VSC6511
Functional Description
The VSC6511 is a multifunction SMPTE-292M device which can be configured for three different modes of
operation: Serializer, Deserializer, or Deserializer/Reclocker. Only one mode is available at a time. A discussion
of the individual building blocks of the device will be followed with specific configurations.
Clock Multiplier Unit (CMU)
The CMU generates the internal serial bit rate clock from the TTL parallel byte rate REFCLK input. The ris-
ing edges of the REFCLK are used by a PLL which multiplies the frequency by a factor of 20. This internal
serial bit rate clock is used by the Serializer, Deserializer and Reclocker sections. An off-chip 0.1uF capacitor
sets the loop bandwidth of the CMU. REFCLK should be a high quality, low jitter signal with sharp rise times in
order to minimize the amount of jitter transferred from the REFCLK through the CMU to the Serializer. This
optimizes the signal quality at the output of the Serializer.
A secondary function of the CMU is to divide the serial bit rate clock by 20 to produce an internal parallel rate
byte clock which is frequency locked and phase aligned to REFCLK. This internal parallel rate byte clock is
used to latch the 20-bit data bus D[19:0] into the input register of the Serializer.
REFCLK is also buffered onto the RCLK output when in Serializer or Reclocker mode. This allows multiple
devices to be daisy-chained in order to simplify REFCLK distribution to an array of devices.
CRC Generator
The twenty bits of transmit data from the input register are fed to dual 10 bit CRC generators that calculate
CRC’s for both the LUMA ( D[19:10] ) and CHROMA ( D[9:0] ) channels independently. The calculation of
CRCs starts after the detection of the SAV sequence and ends after receiving the two line number words (LN0,
LN1) after the EAV sequence. The CRC words (CR0, CR1) are inserted after the LN1 word after the EAV
sequence. The CRC polynomial is CRC(X)= (X18 + X5 + X4 + 1).
The CRC Generator is enabled only in Serializer Mode when CRC is HIGH. In other modes, or if CRC is
LOW, the CRC Generator is disabled and powered down. When CRC is LOW, the data in the CR0 and CR1
locations of the incoming video stream is not overwritten. CRC is a bidirectional pin. Figure 1 shows the CRC
insertion location in more detail.
CLK
DATA IN
CRC
DATA IN
Figure 1: CRC Generation/Insertion Timing Diagram
3FF 000 000 XYZ
SAV SEQUENCE
ACTIVE VIDEO
3FF 000 000 XYZ LN0 LN1 ??? ???
EAV SEQUENCE
3FF 000 000 XYZ
SAV SEQUENCE
ACTIVE VIDEO
3FF 000 000 XYZ LN0 LN1 CR0 CR1
EAV SEQUENCE
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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52311-0, Rev 2.1
6/25/01
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