s MG113P/114P/115P/73P/74P/75P s โโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโโ
FEATURES
โข 0.25ยตm drawn 3-, 4-, and 5-layer metal CMOS
โข Optimized 2.5-V core
โข Optimized 3-V I/O
โข SOG and CSA architecture availability
โข 77-ps typical gate propagation delay (for a 4x-
drive inverter gate with a fanout of 2 and 0 mm
of wire, operating at 2.5 V)
โข Over 5.4M raw gates and 868 I/O pads using
60ยต staggered I/O
โข User-configurable I/O with VSS, VDD, TTL,
3-state, and 1- to 24-mA options
โข Slew-rate-controlled outputs for low-radiated
noise
โข H-clock tree cells which reduces the maximum
skew for clock signals
โข Low 0.2ยตW/MHz/gate power dissipation
โข User-configurable single- and dual-port
memories
โข Specialized IP cores and macrocells including
32-bit ARM7TDMI CPU, phase-locked loop
(PLL), and peripheral component interconnect
(PCI) cells
โข Floorplanning for front-end simulation, back-
end layout controls, and link to synthesis
โข Joint Test Action Group (JTAG) boundary scan
and scan path Automatic Test Pattern
Generation (ATPG)
โข Support for popular CAE systems including
Cadence, IKOS, Mentor Graphics, Model
Technology, Inc. (MTI), Synopsys, and
Viewlogic
2
Oki Semiconductor