VSC9111 View Datasheet(PDF) - Vitesse Semiconductor

Part Name

Description

Manufacturer

VSC9111

SONET/SDH 2.5Gb/s Transport Terminating Transceiver

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

Target Specification

VSC9111

Functional Overview

The VSC9111 is a SONET/SDH transport overhead terminating transceiver. It may be used as an interface

between four STS-12/STM-4 data streams or sixteen STS-3/STM-1 data streams and a single STS-48 data

stream. It also supports transport overhead processing for STS-48c data streams. When used in conjunction with

a high-speed MUX/DEMUX transceiver, this device provides a complete solution for migrating from STS-12/

STS-3 to STS-48 interfaces in SONET/SDH/ATM multiplexers and terminals. The basic features of the receive

and transmit datapaths and features of other interfaces are listed below.

Receive Datapath:

· Performs framing on the A1 and A2 bytes. Supports 12 bit, 24 bit and 48 bit wide A1 A2 framing patterns

· Generates OOF, LOF and LOS alarm status

· Performs SONET descrambling

· Terminates section overhead bytes B1 and J0. Section trace messages are extracted and checked for persis-

tency and mismatch. Provides > 1 min. accumulating counter for B1.

· Terminates line overhead bytes B2, K1, K2, S1 and M1. Detects AIS-L and RDI-L and performs persis-

tency checking (K1, K2, S1). Provides > 1 min. accumulating counters for B2 and M1.

· Extracts and serialises section and line level order wire, user, automatic protection switching, data commu-

nication channels and synchronization channels E1, F1, D1-D3, E2, K1, K2, D4-D12, S1 on dedicated

pins.

· Extracts and serialises entire transport overhead on dedicated pins.

· Performs STS-48 to STS-12/STS-3 byte interleaved demultiplexing.

· Provides STS-3/STS-12 cross-connect functionality

Transmit Datapath:

· Performs STS-12/STS-3 to STS-48 byte interleaved multiplexing

· Provides STS-3/STS-12 cross-connect functionality

· Captures section and line level order wire, user, automatic protection switching, data communication and

synchronization channels E1, F1, D1-D3, E2, K1, K2, D4-D12, S1 from dedicated input pins and

(optionally) inserts these in corresponding transport overhead bytes.

· Captures entire transport overhead from dedicated input pins and (optionally) inserts in transmit transport

overhead.

· Line overhead generation by inserting B2, K1, K2, S1 and M1 and insertion of AIS-L and RDI-L.

· Block/Individual REI-L backreporting

· Section overhead generation by inserting A1, A2, J0/Z0 and B1 bytes

· Performs SONET scrambling

Line Interface:

· Differential 155.52 MHz PECL I/O interface data front-end MUX/DEMUX chipsets

· Provides parity bit and looped clock in Tx path

· Provides Tx and Rx frame pulses and Tx synchronous reset to support STS-192/STM-64 applications

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98

G52199-0, Rev. 1.2

3/8/99

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