VSC9111 View Datasheet(PDF) - Vitesse Semiconductor
Part Name
Description
Manufacturer
VSC9111 Datasheet PDF : 14 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
SONET/SDH 2.5Gb/s
Transport Terminating Transceiver
Target Specification
VSC9111
Pin
RXPRTY_
[A..D][1..4]
LOS
LOF
RSPFP
RSPCLK_1
RSPDAT_1
RSPVALID_1
RSPCLK_2
RSPDAT_2
RSPVALID_2
RTOHCLK
Name
I/O
Parallel Drop Receive
Parity
O
Loss Of Signal
O
Loss Of Frame
O
Receive Special
Purpose Frame Pulse
O
Receive Special
Purpose Clock 1
O
Receive Special
Purpose Data 1
O
Receive Special
Purpose Valid 1
O
Receive Special
Purpose Clock 2
O
Receive Special
Purpose Data 2
O
Receive Special
Purpose Valid 2
O
Receive Transport
Overhead Clock
O
Freq
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Description
STS-3/12/48 Receive Parity.
Parity (even/odd) over the parallel receive STS-3/12/48 data
stream (RXDAT_xN).
In STS-3 mode, RXPRTY_xN is the parity over RXDAT_xN
(2 bit parity).
In STS-12 mode, RXPRTY_x1 is the parity over RXDATxN
(8 bit parity). Optionally, 2 bit parities can be used in this
mode (as described above for STS-3 mode).
In STS-48 mode, RXPRTY_A1 is the parity over RXDAT_xN
(32 bit parity). Optionally, 2 bit or 8 bit parities can be used in
this mode (as described above for STS-3 and STS-12 modes,
respectively).
RXPRTY_xN changes on the falling edge of RXCLK_x.
x = [A,B,C,D], N = [1,2,3,4].
Status signal indicating if Loss Of Signal (LOS) has been
detected. The LOS status is also available in an internal status
register bit. The signal is active high.
Status signal indicating if Loss Of Frame (LOF) has been
detected. The LOF status is also available in an internal status
register bit. The signal is active high.
Frame reference for special purpose serial output ports
RSPDAT_x. The frame pulse is a one clock cycle wide pulse
coincident with the first bit on the serial data streams. Active
high. RSPFP changes on the falling edge of RSPCLK_x.
X = [1,2].
Clock reference for receive special purpose serial output port
1. The clock is a 2.16MHz, 50% duty-cycle signal (optionally
gapped to match the bandwidth of RSPDAT_1.
Data output for special purpose serial port 1. RSPDAT_1
changes on the falling edge of RSPCLK_1.
Valid qualifier for special purpose serial port 1. RSPVALID_1
is asserted (programmable level) when there is valid data on
RSPDAT_1. RSPVALID_1 changes on the falling edge of
RSPCLK_1.
Clock reference for receive special purpose serial output port
2. The clock is a 2.16MHz, 50% duty-cycle signal (optionally
gapped to match the bandwidth of RSPDAT_2.
Data output for special purpose serial port 2. RSPDAT_2
changes on the falling edge of RSPCLK_2.
Valid qualifier for special purpose serial port 2. RSPVALID_2
is asserted (programmable level) when there is valid data on
RSPDAT_2. RSPVALID_2 changes on the falling edge of
RSPCLK_2.
Clock reference for the receive transport overhead port. The
clock is a 38.88MHz, 50% duty-cycle signal.
Page 8
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98
G52199-0, Rev. 1.2
3/8/99
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