MC141524T1 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC141524T1 Datasheet PDF : 12 Pages
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PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations
21, 22, 23, 24, 28, 29,
102, 103, 104, 106, 108, 109, 110
9, 89
16, 97
98
11, 12, 13, 14, 92, 93, 94, 96
8
—
91
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
2, 3, 4, 5, 82, 83, 84, 85
33, 34, 112, 113, 114
7, 15, 25, 39, 52, 60, 68, 76
87, 95, 105, 119, 132, 140, 148, 156
1, 10, 19, 27, 35, 37, 43, 48, 56, 64,
72, 80, 81, 90, 99, 107, 115, 117,
123, 128, 136, 144, 152, 160
6, 17, 18, 20, 26, 30, 31, 32, 36,
86, 88, 100, 101, 111, 116
Symbol
A5 – A17
CAA3,
CAA4
CAB3,
CAB4
CALE
CWE0 –
CWE7
TWE
CS
COE
DQ0 –
DQ63
TIO0 –
TIO7
PD0 –
PD4
VCC3
VCC5
VSS
NC
Type
Input
Input
Description
Address Inputs: These inputs are latched into data RAMs and must
meet setup and hold times. The tag RAM addresses are not latched.
(See Block Diagram).
Cache Address A: Low order address inputs for bursting. Not latched.
Input Cache Address B: Low order address inputs for bursting. Not latched.
Input
Input
Address Latch Enable: Active low signal latches A5 – A17.
Cache Data Write Enable: Active low write signal for data RAMs.
Input
Input
Input
I/O
Tag Write Enable: Active low write signal for tag RAMs.
Chip Select: Active low chip enable for tag and data RAMs. Not used.
Cache Output Enable: Asynchronous active low output enable for data
RAMs.
Data I/O
I/O Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
Presence Detect: See Presence Detect Table.
Supply Power Supply: 3.3 V ± 5%.
Supply Power Supply: 5.0 V ± 5%.
Supply Ground
— No Connection: There is no connection to the module.
MCM64AF32
4
MOTOROLA FAST SRAM
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