ST486SMM View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST486SMM

ST486DX SMM PROGRAMMING MANUAL

STMicroelectronics 

ST486DX - SMM IMPLEMENTATION

Table 2 - 2 CCR2

7

SUSP

6

BWRT

5

BARB

Reg. INDEX = C2h

4

3

2

WT1 HALT LOCK-NW

1

WBAK

0

COP/Reserved

HALT

Suspend on HALT.

HALT = 0:

CPU does not enter suspend mode following execution of a HLT instruction

HALT = 1:

CPU enters suspend mode following execution of a HLT instruction.

SUSP

Enable Suspend Pins.

SUSP = 0:

SUSP# input is ignored and SUSPA# output floats.

SUSP = 1:

SUSP# input and SUSPA# output are enabled.

Table 2 - 1 CCR3

7

6

5

Reserved

Reg. INDEX = C3h

4

3

2

1

NMIEN

0

SMI-LOCK

SMI_LOCK SMM Register Lock.

SMI_LOCK = 0: Any program in normal mode, as well as SMM software, has access to all

Configuration Control Registers.

SMI_LOCK = 1: The following Configuration Control Register bits can not be modified unless

operating in SMM mode:

SMI, SMAC, MMAC, NMIEN, SMI_LOCK, and SMAR register size fields.

NMIEN NMI Enable.

NMIEN = 0:

NMI (Non-Maskable Interrupt) is not recognized during SMM. One occurrence of

NMI is latched and serviced after SMM mode is exited. The NMIEN bit should

be cleared before executing a RSM instruction to exit SMM.

NMIEN = 1:

NMI is enabled during SMM. This bit should only be set temporarily while in the

SMM routine to allow NMI interrupts to be serviced. NMIEN should not be set

16

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