LRS1342 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LRS1342 Datasheet PDF : 24 Pages
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LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
Table 2. Truth Table1
FLASH
SRAM
F-CE
F-RP
F-OE
F-WE
S-CE1
S-CE2
S-OE
S-WE
S-LB
S-UB
DQ0 -
DQ-7
DQ8 -
DQ15
Read
Output Disable
Standby L
H
L
Standby L
H
H
H
X
H
See Note 4
X
X
X See Note 4
DOUT
HIGH-Z
Write
Standby L
H
H
L
X
X
Read
H
H
X
X
L
H
L
H
DIN
See Note 7
Standby
Output
H
H
X
X
L
H
H
H
X
X
HIGH-Z
Disable H
H
X
X
L
H
X
X
H
H
HIGH-Z
Write
H
H
X
X
L
H
L
L
Read
X
L
X
X
L
H
L
H
See Note 7
Reset/Power Down
Output
Disable
X
X
L
L
X
X
X
X
L
L
H
H
H
X
X
H
X
X
H
H
HIGH-Z
HIGH-Z
Write
X
L
X
X
L
H
L
L
See Note 7
Standby
Standby H
H
X
X
X
X
HIGH-Z
See Note 4
See Note 4
Reset/Power Down Standby X
L
X
X
X
X
HIGH-Z
NOTES
2, 3
3
2, 3, 5, 6
3
3
NOTES:
1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics.
2. Refer to the ‘Flash Memory Command Definition’ section for valid
DIN during a write operation.
3. F-WP set to VIL or VIH.
4. SRAM standby mode. See Table 2a.
5. Command writes involving block erase or word write are reliably
executed when F-VPP = VPPH and F-VCC = 2.7 V to 3.6 V. Block
erase or word write with VIH < RP < VHH produce spurious results
and should not be attempted.
6. Never hold F-OE LOW and F-WE LOW at the same time.
7. S-LB, S-UB control mode. See Table 2b.
MODE
Standby
(SRAM)
S-CE1
H
X
X
Table 2a.
PINS
S-CE2
S-LB
X
X
L
X
X
H
S-UB
X
X
H
MODE
(SRAM)
Read/Write
S-LB
L
L
H
Table 2b.
S-UB
L
H
L
PINS
DQ0 - DQ7
DOUT/DIN
DOUT/DIN
HIGH-Z
DQ8 - DQ15
DOUT/DIN
HIGH-Z
DOUT/DIN
Table 3. Command Definition for Flash Memory1
COMMAND
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word Write
Block Erase and Word
Write Suspend
Block Erase and Word
Write Resume
BUS CYCLES
REQUIRED
1
≥2
2
1
2
2
FIRST BUS CYCLE
OPERATION2 ADDRESS3 DATA3
Write
XA
FFH
Write
XA
90H
Write
XA
70H
Write
XA
50H
Write
BA
20H
Write
WA
40H or 10H
SECOND BUS CYCLE
OPERATION2 ADDRESS3 DATA3
Read
Read
IA
ID
XA
SRD
Write
Write
BA
D0H
WA
WD
NOTES
4
5
5
1
Write
XA
B0H
5
1
Write
XA
D0H
5
NOTES:
1. Commands other than those shown in table are reserved by
SHARP for future device implementations and should not be used.
2. BUS operations are defined in Table 2.
3. XA = Any valid address within the device;
IA = Identifier code address;
BA = Address within the block being erased;
WA = Address of memory location to be written;
SRD = Data read from status register, see Table 6;
WD = Data to be written at location WA. Data is latched on the
rising edge of F-WE or F-CE (whichever goes high first);
ID = Data read from identifier codes.
4. See Table 4 for Identifier Codes.
5. See Table 5 for Write Protection Alternatives.
4
Data Sheet
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