TDA9615 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TDA9615

13.2 V, audio processor for VHS hi-fi

Philips Electronics 

Philips Semiconductors

Audio processor for VHS hi-fi

Preliminary specification

TDA9615H

I2C-BUS PROTOCOL

Addressing and data bytes

For programming the device (write mode) seven data byte registers are available; they are addressable via eight

subaddresses. Automatic subaddress incrementing enables the writing of successive data bytes in one transmission.

During power-on, data byte registers are reset to a default state by use of a Power On Reset (POR) circuit which signal

is derived from the internally generated I2C-bus supply voltage (V5OUT; pin 38). For reading from the device (read mode)

one data byte register is available without subaddressing.

Table 1 TDA9615H addresses and data bytes

DATA BYTE

ADDRESS

Write mode

Slave address byte (B8H)

1

0

1

1

1

0

0

Subaddress bytes (00H to 07H) 0(1)

0(1)

0(1)

0(1)

0

0 or 1 0 or 1

Control byte (subaddress 00) AFM

DOC

SHH

DETH NTSC MUTE STBP

Select byte (subaddress 01) DOS1 DOS0 s5

s4

NIL3 NIL2 NIL1

Input byte (subaddress 02)

i7

IS2

IS1

IS0

NS2

NS1

NS0

Output byte (subaddress 03) LOH

OSN OSR OSL

EOS

LOS

DOS

Left volume byte

(subaddress 04)

I7

VLS

VL5

VL4

VL3

VL2

VL1

Right volume byte

(subaddress 05)

r7

VRS

VR5

VR4

VR3

VR2

VR1

Volume byte (subaddress 06) simultaneous loading of subaddress 04 and subaddress 05 register

Power byte (subaddress 07) CALS VCCH TEST PORR p3

p2

p1

Read mode

Slave address byte (B9H)

Read byte

1

0

1

1

1

0

0

CALR AUTN 0(2)

POR

0(2)

1(2)

0(2)

0

0 or 1

STBA

NIL0

i0

RFCM

VL0

VR0

p0

1

0(2)

Notes

1. Use of subaddress F0H to F7H (1111 0XXX) instead of 00H to 07H (0000 0XXX) disables the automatic subaddress

incrementing allowing continuous writing to a single data byte register.

2. The state of unused read bits are not reliable; their state may change during development.

Table 2 Status of data bytes after POR

DATA BYTE

Control byte

Select byte

Input byte

Output byte

Left volume byte

Right volume byte

Power byte

1

0

0

0

0(1)

0

0

0

0(1)

1

0(1)

1

0

0

ADDRESS

0

0

1

1

0

0

1(1)

1(1)

0

0

0

0

0

0

1

1

1

0(1)

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0(1)

0(1)

0(1)

0(1)

Note

1. For eventual future compatibility it is advised to keep unused write bits equal to POR state.

1997 Jun 16

9

Share Link: