STLC1502 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC1502

VOICE OVER IP PROCESSOR

STMicroelectronics 

STLC1502

• The memory blocks are attached to the AHB bus so ARM code can run at maximum speed.

• An internal ROM is used to store boot code that polls serial peripherals (I2C EEPROM, UART) and

HPI for code download in external RAM. After download, the control is given to code in external

RAM.

• An internal RAM is used to store ARM7 interrupt vectors and some data (network frames)

• Four external memory types can be connected.

• Flash

• SRAM

• DRAM (SDRAM or EDO)

• Serial EEPROM

• Flash, SRAM, DRAM share the same 32 bits data bus and 32 bits address bus. Little/Big endian

mode is software programmable for the DRAM memory controller. Serial EEPROM can be con-

nected to the I2C bus.

• The chip provides the option of booting from Flash or from serial EEPROM, by selection from an

external BOOT_SEL pin. So different memory configurations are possible depending on the applica-

tion:

1. Flash, DRAM: The boot code including BOOTP and TFTP is stored in Flash. Application can be

stored in flash also, or can be downloaded into DRAM from Ethernet Network or UART.

2. EEPROM, DRAM: The boot is performed from internal ROM. The ROM code loads the code stored

in EPROM that includes BOOTP and TFTP. Application code will be downloaded into DRAM from

Ethernet or UART.

3. Flash, DRAM, EEPROM: It is like case 1, but has more flexibility. The EEPROM can be used to store

Network parameter data (MAC address) and other specific board data, so the code to store in flash is

the same for all the platforms, and you do not need to split the flash in a permanent storage area and

in an upgradable storage area. The EEPROM can also be used to allow the programming of the flash

the first time with a code downloaded from Ethernet Network.

4. DRAM: The boot is performed from internal ROM. The application code is downloaded from the host

processor through the HPI interface. To access external memory bus an internal decoder is imple-

mented, that can select different external memory devices. 32 bits data bus is provided with the pos-

sibility to select external accesses at 16 and 8 bits for each memory bank. For example the flash can

be at 16 bits and the DRAM at 32 bits. There are 3 chip select available for static memory (4Mbytes

each), 4 chip selects for dynamic memory (8Mbytes each).

5.1 ARM Memory Map

The ARM microprocessor sees 5 main memory areas.

Actually the memory map depends on the phase the microprocessor is working on:

• Boot from internal ROM phase (REMAP=0 and BOOT_SEL=0);

• Boot from external Flash phase (REMAP=0 and BOOT_SEL=1);

• Operating phase (REMAP=1).

The first two phases are alternative (only one of them happens at the power on reset, while the third happens

after the boot.

6.0 AHB Bus

AHB Bus is a 32 bits data and 32 bits address bus.

6.1 Internal RAM

An internal Static RAM 2048x 32 is mapped starting at address 0x0 in operational mode and is used for ARM

interrupt vector tables.

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