VSC9112 View Datasheet(PDF) - Vitesse Semiconductor

Part Name

Description

Manufacturer

VSC9112

STS-48c Physical Layer Packet/ATM Over SONET/SDH Device

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

STS-48c Physical Layer

Packet/ATM Over SONET/SDH Device

Datasheet

VSC9112

Transmit Packet Processor (TPP)

• The inserted HDLC Flag Sequence byte and the minimum number of Flag Sequence bytes separating

HDLC frames are programmable.

• The insertion of the Address and Control fields can be controlled by the HDLC Address-and-Control-

Field-Compression mechanism.

• The Address Field inserted after the beginning Flag Sequence is programmable.

• The Control Field inserted after the the Address Field is programmable.

• The Frame Check Sequence (FCS) can be generated using either a 16-bit, CRC-CCITT generating poly-

nomial 1 + x5 + x12 + x16, or a 32-bit CRC-32 generating polynomial 1 + x + x2 + x4 + x5 + x7 + x8 + x10

+ x11 + x12 + x16 + x22 + x23 + x26 + x32.

• Octet Stuffing, or “escaping”, can be applied after the FCS generation and partial scrambling, if enabled.

The Control Escape byte and the Octet Stuffing Masking byte are programmable. The Asyc-Control-

Character-Map (ACCM) can accommodate a maximum of 5 byte values. Each value can be individually

enabled/disabled.

• The transmitted data is scrambled with a self-synchronizing scrambler (SSS) polynomial 1 + x43. Full

and/or partial scrambling can be independently enabled/disabled.

• The PPP Protocol Field can be generated internally or extracted from the transmit FIFO. The size and

value of the inserted Protocol Field are programmable when generated internally.

• The Tx FIFO is programmable in the range from 1 to 4095 words or 16380 bytes of data storage. All

valid packet bytes stored in the Tx FIFO are read out and mapped into the PPP Protocol/Information

Fields of generated PPP/HDLC frames.

• Two Tx PIF packet transfer modes are supported: packet transfer mode and word transfer mode.

• The TXF_ERR signal is provided to force insertion of errors into the FCS, or to force abort the transmit-

ted HDLC frame.

• It is possible to force XOR'ing of the transmitted Address, Control or Protocol Fields with a programma-

ble mask value via the CPU interface for diagnostic purposes.

• The following statistics are provided in the performance monitoring 32-bit counters:

• Bytes read from Tx FIFO

• Transmitted good HDLC frames (non-aborted, non-FCS errored)

• Transmitted Aborted HDLC frames

• Transmitted FCS Errored HDLC frames

• Long packets read from Tx FIFO

• Short packets read from Tx FIFO

• Transmitted empty HDLC frames

• Bytes pre octet-stuffing (excluding Abort sequences)

• Bytes post octet-stuffing (excluding Abort sequences)

Page 6

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52210-0, Rev. 4.3

3/30/00

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