W83977ATF View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

W83977ATF

WINBOND I/O

Winbond 

W83977ATF

TABLE OF CONTENTS

GENERAL DESCRIPTION.................................................................................................................................1

FEATURES ............................................................................................................................................................ 2

PIN CONFIGURATION ......................................................................................................................................5

1.0 PIN DESCRIPTION......................................................................................................................................6

1.1 HOST INTERFACE...............................................................................................................................................6

1.2 GENERAL PURPOSE I/O PORT............................................................................................................................9

1.3 SERIAL PORT INTERFACE.................................................................................................................................10

1.4 INFRARED INTERFACE .....................................................................................................................................11

1.5 MULTI-MODE PARALLEL PORT .......................................................................................................................11

1.6 FDC INTERFACE..............................................................................................................................................16

1.7 KBC INTERFACE .............................................................................................................................................17

1.8 POWER PINS ................................................................................................................................................18

1.9 ACPI INTERFACE ............................................................................................................................................18

2.0 FDC FUNCTIONAL DESCRIPTION .......................................................................................................19

2.1 W83977ATF FDC ..........................................................................................................................................19

2.1.1 AT interface .............................................................................................................................................19

2.1.2 FIFO (Data) ............................................................................................................................................19

2.1.3 Data Separator ........................................................................................................................................20

2.1.4 Write Precompensation ...........................................................................................................................20

2.1.5 Perpendicular Recording Mode ..............................................................................................................20

2.1.6 FDC Core ................................................................................................................................................21

2.1.7 FDC Commands ......................................................................................................................................21

2.2 REGISTER DESCRIPTIONS.................................................................................................................................31

2.2.1 Status Register A (SA Register) (Read base address + 0) .......................................................................31

2.2.2 Status Register B (SB Register) (Read base address + 1) .......................................................................33

2.2.3 Digital Output Register (DO Register) (Write base address + 2) ...........................................................35

2.2.4 Tape Drive Register (TD Register) (Read base address + 3)..................................................................35

2.2.5 Main Status Register (MS Register) (Read base address + 4) ................................................................36

2.2.6 Data Rate Register (DR Register) (Write base address + 4)...................................................................36

2.2.7 FIFO Register (R/W base address + 5)...................................................................................................38

2.2.8 Digital Input Register (DI Register) (Read base address + 7)................................................................40

2.2.9 Configuration Control Register (CC Register) (Write base address + 7)...............................................41

3.0 UART PORT.................................................................................................................................................43

3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ............................................... 43

3.2 REGISTER ADDRESS.........................................................................................................................................43

3.2.1 UART Control Register (UCR) (Read/Write) ..........................................................................................43

3.2.2 UART Status Register (USR) (Read/Write)..............................................................................................45

3.2.3 Handshake Control Register (HCR) (Read/Write) ..................................................................................46

Publication Release Date: October 2001

-I-

Revision 0.53

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