GS841E18AB-133I View Datasheet(PDF) - Giga Semiconductor
Part Name
Description
Manufacturer
GS841E18AB-133I Datasheet PDF : 29 Pages
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PBGA Pin Description
Pin Location
P4, N4, R2, C3, B3, C2, A2, A3, A5, A6, T6, C5,
R6, T5, T2, T3, B5, C6
K4
M4
L5
G3
H4
E4, B2, B6
F4
G4
A4, B4
P7, N6, L6, K7, H6, G7, F6, E7, D1, E2, G2, H1,
K2, L1, M2, N1
D6, P2
M6
P6
N7
T7
R5
R3
U2
U3
U5
U4
C4, J2, J4, J6, R4
D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5,
N3, N5, P3, P5
A1, A7, F1, F7, J1, J7, M1, M7, U1, U7
B1, B7, C1, C7, D2, D4, D7, E1, E6, F2, G1, G5,
G6, H2, H7, J3, J5, K1, K6, L2, L3, L4, L7, N2,
P1, RR1, R7, T1, T4, U6
Symbol
A0–A17
CLK
BWE
BW1
BW2
GW
CE1,CE2, CE3
OE
ADV
ADSP, ADSC
DQ1–DQ16
DQP1–DQP2
MATCH
MOE
DE
ZZ
FT
LBO
TMS
TDI
TDO
TCK
VDD
VSS
VDDQ
NC
GS841E18AT/B-166/150/130/100
Description
Address Input Signals—Inputs are registered and must meet
setup and hold times, as specified on page 11.
Clock Input Signal
Byte Write Enable Signal—The byte write enable signal needs to
be combined with one of the four byte write signals for a write
operation to occur.
Byte Write signal for data outputs 1 thru 8
Byte Write signal for data outputs 9 thru 16
Global Write Enable
Chip Enables
Output Enable
Burst address advance
Address status signals
Data Input and Output pins
Parity Input and Output pins
Match Output
Match Output Enable
Data Enable—Data input registers are updated only when DE is
active.
Power down control—Application of ZZ will result in a low
standby power consumption.
Flow Through or Pipeline mode
Linear Order Burst mode
Test Mode Select
Test Data In
Test Data Out
Test Clock
3.3 V power supply
Ground
2.5 V/3.3 V output power supply
No Connect
Rev: 1.00 10/2001
5/29
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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