BA7207AK View Datasheet(PDF) - ROHM Semiconductor

Part Name

Description

Manufacturer

BA7207AK

SECAM chroma signal processor for VHS VCRs

ROHM Semiconductor 

Video ICs

BA7207AS / BA7207AK

•Circuit operation

(1) Recording system (REC)

The input to REC IN is passed through the 4.3MHz BPF-A to remove unwanted frequency components, and is flat-

tened by REC BELL which has an anti-bell characteristic. The flattened signal is wave-shaped by the limiter amplifer,

and processed by the divide-by-four and sync gate circuits. Finally, unwanted frequency components are removed

by the 1.1MHz BPF and the REC EQ prepares the signal for recording playback and the signal is output on REC

OUT. Refer to Fig. 3.

Composite video signal

100pF

1

4.3MHz

BPF - A

( 40 )

REC

BELL

26

24 LIMAMP ÷ 4

( 31 ) ( 27 )

BA7207AS

(BA7207AK)

Fig. 3

REC

SYNC

GATE

1.1MHz

BPF

RECOUT

REC

EQ

AMP

28

( 33 )

(2) Playback system (PB)

The input to PB IN is passed through the 1.1MHz BPF to remove unwanted frequency components, and is flattened

by the PB EQ circuit. The amplitude of the flattened signal fixed by the 1st-stage limiter amplifier, and the frequency

is multiplied by four by the multiplier circuit. Unwanted frequency components generated by the multiplier circuit are

removed by the 2.2MHz BPF and 4.3MHz BPF-A. The signal is wave-shaped by the limiter amplifier, and has gate

applied to it by the sync gate circuit then is passed through the 4.3MHz BPF-B to remove unwanted frequency com-

ponents. The PB BELL circuit restores the original bell characteristic and the signal is output on PB OUT. Refer to

Fig. 4.

RF chroma signal

LPF

fcԼ2.2MHz

18

AMP

1.1MHz

BPF

PB

EQ

LIMAMP

×2

( 20 )

2.2MHz

BPF

26

( 31 )

24 LIMAMP

( 27 )

PB

SYNC

GATE

4.3MHz

BPF - B

PB

BELL

AMP

6

(2)

BA7207AS

(BA7207AK)

×2

4.3MHz

BPF - A

TRAP

8

AMP

( 5)

PBOUT

11

( 10 )

(3) Sync gate timing circuit

Fig. 4

REC and PB SYNC gate operation is as follows. The gate closes closes in synchronous with the SYNC IN input

pulse during the synchronous signal pulse (SYNC) horizontal scan interval (64µs period). During vertical retrace

(32µS period), the input pulse period becomes shorter than the horizontal scan interval. This is detected by the built-

in vertical synchronous detector circuit which closes the gate. Refer to Fig. 5.

SYNCIN

Horizontal scan interval

64µs

4µs

32µs

Vertical retrace interval

REC / PBOUT,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

Fig. 5

12

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