HEF4029B View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

HEF4029B

Synchronous up/down counter, binary/decade counter

Philips Electronics 

Philips Semiconductors

Synchronous up/down counter,

binary/decade counter

Product specification

HEF4029B

MSI

DESCRIPTION

The HEF4029B is a synchronous edge-triggered up/down

4-bit binary/BCD decade counter with a clock input (CP),

an active LOW count enable input (CE), an up/down

control input (UP/DN), a binary/decade control input

(BIN/DEC), an overriding asynchronous active HIGH

parallel load input (PL), four parallel data inputs (P0 to P3),

four parallel buffered outputs (O0 to O3) and an active

LOW terminal count output (TC).

Information on P0 to P3 is asynchronously loaded into the

counter while PL is HIGH, independent of CP.

The counter is advanced one count on the LOW to HIGH

transition of CP when CE and PL are LOW. The TC signal

is normally HIGH and goes LOW when the counter

reaches its maximum count in the UP mode, or the

minimum count in the DOWN mode provided CE is LOW.

Fig.1 Functional diagram.

HEF4029BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4029BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4029BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

Fig.2 Pinning diagram.

PINNING

PL

P0 to P3

BIN/DEC

UP/DN

CE

CP

O0 to O3

TC

parallel load input

parallel data inputs

binary/decade control input

up/down control input

count enable input (active LOW)

clock input (LOW to HIGH, edge triggered)

buffered parallel outputs

terminal count output (active LOW)

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

2

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