CXD2450R View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXD2450R

Timing Generator for Progressive Scan CCD Image Sensor

Sony Semiconductor 

CXD2450R

3) Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD2450R at the timing shown in 2) above. However, one

exception to this is when the data such as SSGSEL and STB is loaded to the CXD2450R and controlled at the

rising edge of SEN. For STB, see control data D62 to D63 STB in "Description of Operation".

SEN

Output signal

0.8VDDd

tpdPULSE

Symbol

tpdPULSE

(Within the recommended operating conditions)

Definition

Min. Typ. Max. Unit

Output signal delay, activated by the rising edge of SEN

5

100 ns

4) RST loading characteristics

RST

Symbol

tw1 RST pulse width

0.2VDDd

Definition

0.8VDDd

tw1

(Within the recommended operating conditions)

Min. Typ. Max. Unit

35

ns

5) Phase discrimination characteristics using FRI and HRI input

When the HRI logic level is low tpd1 after

the falling edge of FRI

When the HRI logic level is high tpd1 after

the falling edge of FRI

FRI 0.2VDDd

HRI

tpd1

FRI

0.2VDDd

HRI

tpd1

The field is discriminated as an ODD field .

The field is discriminated as an EVEN field .

(Within the recommended operating conditions)

Symbol

Definition

Min. Typ. Max. Unit

tpd1 Field discrimination clock phase, activated by the falling edge of FRI 1100

1300 ns

– 10 –

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