A16450 View Datasheet(PDF) - Altera Corporation
Part Name
Description
Manufacturer
A16450 Datasheet PDF : 16 Pages
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a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 1 describes the input and output ports of the a16450.
Table 1. a16450 Ports (Part 1 of 2)
Name
nads
clk
cs0
cs1
ncs2
ncts
ndcd
ndsr
mr
rclk
rd
nrd
nri
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Polarity
Description
Low
–
High
High
Low
Low
Low
Low
High
–
High
Low
Low
Address strobe. Enable signal to the address input receiver. The positive
edge of nads latches the register address bus into the address input
register.
Clock. Provides the master timing reference to the a16450.
Chip select 0. The a16450 is selected when cs0, cs1, and ncs2 are
asserted, which permits read and write transactions to internal registers.
Chip select 1. The a16450 is selected when cs0, cs1, and ncs2 are
asserted, which permits read and write transactions to internal registers.
Chip select 2. The a16450 is selected when cs0, cs1, and ncs2 are
asserted, which permits read and write transactions to internal registers.
Clear to send. Indicates that the modem is ready to exchange data. A
change in input state from low to high is recorded in bit 0 of the modem
status register. If the modem status interrupt is enabled when ncts
changes state, an interrupt is generated. This input’s complement is
recorded in bit 4 of the modem status register.
Data carrier detect. Indicates that the modem or data set detected a data
carrier. A change in input state is recorded in bit 3 of the modem status
register. If the modem status interrupt is enabled when ndcd changes
state, an interrupt is generated. This input’s complement is recorded in bit 7
of the modem status register.
Data set ready. Indicates that the modem or data set is ready to establish
the communications link with the a16450. A change in input state is
recorded in bit 1 of the modem status register. If the modem status interrupt
is enabled when ndsr changes state, an interrupt is generated. This input’s
complement is recorded in bit 5 of the modem status register.
Master reset. Clears all registers (except the receiver buffer, transmitter
holding, and divisor registers) to their initial state. Resets control logic to
initial state.
Receiver clock. Operates at 16 times the baud rate clock.
Read control. When rd or nrd is asserted and the a16450 is selected,
read transactions from internal registers are possible.
Read control. When rd or nrd is asserted and the a16450 is selected,
read transactions from internal registers are possible.
Ring indicator. Indicates that the modem or data set detected the ring
signal. A change in input state is recorded in bit 2 of the modem status
register. If the modem status interrupt is enabled when nri changes state,
an interrupt is generated. This input’s complement is recorded in bit 6 of the
modem status register.
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Altera Corporation
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