A16450 View Datasheet(PDF) - Altera Corporation

Part Name

Description

Manufacturer

A16450

Universal Asynchronous Receiver/Transmitter

Altera Corporation 

a16450 Universal Asynchronous Receiver/Transmitter Data Sheet

Register Address Map

The state of the a[2..0] inputs determines which internal register the

microprocessor addresses. See Table 2.

The divisor register access bit (drab) allows access to the divisor register.

The drab is bit 7 of the line control register.

Table 2. Register Address Map

drab (1) a2 a1 a0

Register

0

0

0

0 Receiver buffer register—read only

Transmitter holding register—write only

1

0

0

0 Divisor register (LSB)

0

0

0

1 Interrupt enable register

1

0

0

1 Divisor register (MSB)

X

0

1

0 Interrupt ID register

X

0

1

1 Line control register

X

1

0

0 Modem control register

X

1

0

1 Line status register

X

1

1

0 Modem status register

X

1

1

1 Scratchpad register

Note:

(1) The X indicates “don’t care.”

Registers

The a16450 MegaCore function contains the following registers:

s Receiver buffer

s Transmitter holding

s Divisor

s Interrupt enable

s Interrupt identification

s Line control

s Modem control

s Line status

s Modem status

s Scratchpad

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