AD698 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD698 Datasheet PDF : 12 Pages
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VOUT
=
2 × RS
RG + 1
× VIN
Solving for VOUT/VIN = 400 and setting RG = 100 Ω then:
RS = [400 – 1] × RG/2 = 19.95 kΩ
Choose an oscillator amplitude that is in the range of 1 V to
3.5 V rms. For an input excitation level of 3 V rms, the output
signal from the amplifier gain stage will be 3.5 V rms × 0.8 V or
2.4 V rms, which is in the acceptable range.
AD698
Since A/B is known, the value of R2, the output FS resistor may
be chosen by the formula:
VOUT = A/B × 500 µA × R2
For a 10 V output at FS, with an A/B of 0.8; solve for R2.
R2 = 10 V [0.8 × 500 µA] = 25.0 kΩ
This will result in a VOUT of 10 V for a full-scale signal from the
bridge. The other components, C1, C2, C3, C4 may be selected
by following the guidelines on general device operation men-
tioned earlier.
If a gain trim is required, then a trim resistor can be used to ad-
just either R2 or RG. Bridge offsets should be adjusted by a trim
network on the OFFSET 1 and OFFSET 2 pins of the AD698.
+15V
–15V
6.8µF
RESISTORS,
INDUCTORS
OR CAPACITORS
A1
RS
RG
RS
A2
DUAL
OP AMP
6.8µF
100nF
100nF
R1
C1
C2
1 –VS
AD698
+VS 24
R4
2 EXC1 OFFSET1 23
R3
3 EXC2 OFFSET2 22
SIGNAL
REFERENCE
4 LEV1
SIG REF 21
5 LEV2
SIG OUT 20
R2
RL
VOUT
6 FREQ1 FEEDBACK 19
C4 1000pF
7 FREQ2 OUT FILT 18
8 BFILT1
9 BFILT2
AFILT1 17
C3
AFILT2 16
10 –BIN
–ACOMP 15
11 +BIN
12 –AIN
+ACOMP 14
+AIN 13
A
B
PHASE
LAG/LEAD
NETWORK
C
D
PHASE LAG
A
B
C
PHASE LEAD
A
B
RT
RS
RS
RT
RS
C
C
C
D
C
D
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = RS// (RS + RT)
Figure 20. AD698 Interconnection Diagram for AC Bridge Applications
REV. B
–11–
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