1Semiconductor
PEDL60852-01
ML60852
DATA SHEET REVISION HISTORY
From Ver. 0.32 to Ver. 0.40 - March 25, 1999
• Changed the FIFO access time in the timing chart from 42ns to 63ns.
• Changed the read data delay time in the timing chart from 25ns to 46ns.
• Added functions to the higher order three bits of the DMA control register.
• Added restrictions on the use of the DMA control register.
• Discontinued supporting the 1K byte packet size in EP4.
• Corrected the data packet transmission and reception procedure during isochronous transfer in paragraph (6) of
the FUNCTION DESCRIPTION.
• Changed the maximum packet size (FIFO size) of EP0 and EP3 to 32 bytes.
• Added remote wakeup bit in the system control register.
• Changed the bit position of the receive/transmit packet ready bits in the EP status registers.
• Changed the bit positions of the EP0 receive/transmit packet ready interrupt status/enable bits of the interrupt
status/enable register 1.
• Added the function of conforming to protocol stall in the stall bit of the EP0 control register.
• Added anew the MSB part in the EP4,5 payload/byte count register.
• Changed the specifications of the interrupt statuses related to USB bus reset, suspend, and awake.
From Ver. 0.40 to Ver. 0.50 - June 25, 1999
• Changed 48-pin TQFP to 56-pin LGA.
• Changed PIN CONGURATION.
• Changed the set value of the EP mode bit of the system control register.
• Added the PLL enable bit in D5 of the system control register.
• Added the PLL multiplication factor selection bit in D6 of the system control register.
• Corrected other wrong Description.
From Ver. 0.50 to Ver. 0.51 - July 13, 1999
• Added 56-pin LGA pin configration.
• Corrected the figure.
• Description of ALE/PUCTL: Corrected the bit map position of the SYSCON register.
• Changed the description - End point and De-packeting
• Reporting handshake is ACK ... <- Deleted ACK.
• Added missing entry of the byte count register.
• Corrected spelling mistake.
• Corrected the bit map position of EPnSTAT.
• Corrected the bit map position of EPnSTAT.
• Corrected the bit map position of the SYSCON register.
• Deleted the device state register.
• Added description.
• Corrected the shift in the figure.
• Changed the expression.
• Added description.
• Changed the expression.
• Added "Writing of the data sequence bit is invalid".
• Changed from (R/Set) to (R/Reset) and from (R/Reset) to (R/Set), changes the name of EP0 stage.
• nak to NAK
• Corrected the drawing.
• Changed from (R/Set) to (R/Reset) and from (R/Reset) to (R/Set)
• Changed from (R/Set) to (R/Reset) and from (R/Reset) to (R/Set)
• Deleted the device state register.
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