UT06MRA050 View Datasheet(PDF) - Aeroflex UTMC

Part Name

Description

Manufacturer

UT06MRA050

UT0.6µCRH Commercial RadHard™ Gate Array Family

Aeroflex UTMC 

Extensive Cell Library

The UT0.6CRH family of gate arrays is supported by an exten-

sive cell library that includes SSI, MSI, and 54XX-equivalent

functions, as well as RAM and other library functions. User-se-

lectable options for cell configurations include scan for all

register elements, as well as output drive strength. Aeroflex’s core

library includes the following functions:

 Intel® 80C31 equivalent

 Intel® 80C196 equivalent

 MIL-STD-1553 functions (RTI)

 MIL-STD-1750 microprocessor

 Standard microprocessor peripheral functions

 Configurable RAM (SRAM, DPSRAM)

 RISC Microcontroller

 USART (82C51)

 EDAC

 Aeroflx Gaisler IP

Refer to Aeroflex’s UT0.6CRH Design Manual for complete

cell listing and details.

I/O Buffers

The UT0.6CRH gate array family offers up to 544 signal I/O

locations (note: device signal I/O availability is affected by pack-

age selection and pinout.) The I/O cells can be configured by the

user to serve as input, output, bidirectional, three-state, or addi-

tional power and ground pads. Output drive options range from

2 to 12mA. To drive larger off-chip loads, output drivers may be

combined in parallel to provide additional drive up to 24mA.

Other I/O buffer features and options include:

 Slew rate control

 Pull-up and pull-down resistors

 TTL, CMOS, and Schmitt levels

 Cold sparing

 Voltage translation

- 5V bus to 3.3V bus

- 3.3V bus to 5V bus

Clock Driver Distribution

Aeroflex design tools provide methods for balanced clock distri-

bution that maximize drive capability and minimize relative clock

skew between clocked devices.

Speed and Performance

Aeroflex specializes in high-performance circuits designed to op-

erate in harsh military and radiation environments. Table 3

presents a sampling of typical cell delays.

Note that the propagation delay for a CMOS device is a function

of its fanout loading, input slew, supply voltage, operating tem-

perature, and processing radiation tolerance. In a radiation

environment, additional performance variances must be consid-

ered. The UT0.6CRHarray family simulation models account

for all of these effects to accurately determine circuit performance

for its particular set of use conditions.

Power Dissipation

Each internal gate or I/O driver has an average power consump-

tion based on its switching frequency and capacitive loading.

Radiation-tolerant processes exhibit power dissipation that is typ-

ical of CMOS processes. For a rigorous power estimating

methodology, refer to the Aeroflex UT0.6CRH Design Manual

or consult with an Aeroflex Applications Engineer.

Typical Power Dissipation

1.1W/Gate-MHz@5.0V 0.4W/Gate-MHz@3.3V

JTAG Boundary-Scan

The UT0.6CRH arrays provide for a test access port and bound-

ary-scan that conforms to the IEEE Standard 1149.1 (JTAG).

Some of the benefits of this capability are:

 Easy test of complex assembled printed circuit

boards

 Gain access to and control of internal scan paths

 Initiation of Built-In Self Test

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