ADP3155 View Datasheet(PDF) - Analog Devices
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ADP3155 Datasheet PDF : 14 Pages
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ADP3155
high side FET, however, is turned on with only 12 V – 5 V = 7 V.
Checking the typical output characteristics of the device in the
data sheet shows that for an output current of 10 A, and at a
VGS of 7 V, the VDS is 0.15 V. This gives an RDS(ON) only slightly
above the one specified at a VGS of 10 V, so the resistance in-
crease due to the reduced gate drive can be neglected. The
specified RDS(ON) at the expected highest FET junction tempera-
ture of +140°C must be modified by an RDS(ON) multiplier,
using the graph in the data sheet. In this case:
RDS(ON)MULT = 1.7
Using this multiplier, the expected RDS(ON) at +140°C is 1.7 ×
14 mΩ = 24 mΩ.
The high side FET dissipation is:
PDFETHS = IRMSHS2RDS(ON) + 0.5 VINILPEAKQGfMIN/IG ~ 3.72 W
where the second term represents the turn-off loss of the FET.
(In the second term, QG is the gate charge to be removed from
the gate for turn-off and IG is the gate current. From the data
sheet, QG is about 50 nC–70 nC and the gate drive current
provided by the ADP3155 is about 1 A.)
The low side FET dissipation is:
PDFETLS = IRMSLS2 RDS(ON) = 1.7 W
(Note that there are no switching losses in the low side FET.)
To maintain an acceptable MOSFET junction temperature,
proper heat sinks should be used. The Thermalloy 6030 heat
sink has a thermal impedance of 13°C/W with convection cool-
ing. With this heat sink, the junction-to-ambient thermal imped-
ance of the chosen high side FET θJAHS will be 13°C/W (heat
sink-to-ambient) + 2°C/W (junction-to-case) + 0.5°C/W (case-
to-heat sink) = 15.5°C/W.
At full load, and at +50°C ambient temperature, the junction
temperature of the high side FET is:
TJHSMAX = TA + θJAHS PDFETHS = +105°C
The same heat sink may be used for the low side FET, e.g., the
Thermalloy type 7141 (θ = 20.3°C/W). With this heat sink, the
junction temperature of the low side FET is:
TJLSMAX = TA + θJALS PDFETLS = +106° C
All of the above-calculated junction temperatures are safely
below the +175°C maximum specified junction temperature of
the selected FETs.
The maximum operating junction temperature of the ADP3155
is calculated as follows:
TJICMAX = TA + θJA (IICVCC + PDR)
where θJA is the junction-to-ambient thermal impedance of the
ADP3155 and PDR is the drive power. From the data sheet, θJA
is equal to 110°C/W and IIC = 2.7 mA. PDR can be calculated as
follows:
PDR = (CRSS + CISS)VCC2 fMAX = 307 mW
The result is:
TJICMAX = +86°C
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of VOUT/
VlN. To keep the input ripple voltage at a low value, one or more
capacitors with low equivalent series resistance (ESR) and ad-
equate ripple-current rating must be connected across the input
terminals. The maximum rms current of the input bypass
capacitors is:
ICINRMS = 0.5 IOMAX = 7 A rms
For an FA-type capacitor with 2700 µF capacitance and
10 V voltage rating, the ESR is 34 mΩ and the allowed ripple
current at 100 kHz is 1.94 A. At +105°C, at least four such
capacitors must be connected in parallel to handle the calculated
ripple current. At +50°C ambient, however, a higher ripple
current can be tolerated, so three capacitors in parallel are
adequate.
The ripple voltage across the three paralleled capacitors is:
VCINRPL = IOMAX [ESRIN/3 +DMAXHF/(3 CIN fMIN )] =
140 mV p-p
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/µs, an additional
small inductor (L > 1.7 µH @ 10 A) should be inserted between
the converter and the supply bus (see Figure 2).
Feedback Loop Compensation Design for Active Voltage
Positioning
Optimized compensation of the ADP3155 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
To correctly implement active voltage positioning, the low fre-
quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. This can be achieved by having a single
pole roll-off of the voltage gain of the gm error amplifier, where
the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single pole roll-off requires that the gm
amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. The required resistor value can be
calculated from the equation:
where:
RC
=
275 kΩ ×
275 kΩ –
RtTOTAL
RtTOTAL
RtTOTAL
=
16.4
kΩ × RCS ×
VHI –VLO
IOMAX
and where the quantities 16.4 kΩ and 275 kΩ are characteristic
of the ADP3155 and the value of the current sense resistor, RCS,
has already been determined as above.
Although a single termination resistor equal to RC would yield
the proper voltage positioning gain, the dc biasing of that resis-
tor would determine how the regulation band is centered (i.e.,
offset). Note that sometimes the specified regulation band is
asymmetrical with respect to the nominal VID voltage. With the
ADP3155, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the
–10–
REV. A
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