MINI51 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MINI51

32-BIT MICROCONTROLLER - ARM Cortex™-M0

Unspecified 

NuMicro™ Mini51 Technical Reference Manual

List of Figures

Figure 3.1-1 NuMicro Mini51 Series Product Selection Guide.................................................... 14

Figure 3.2-1 NuMicro Mini51 Series LQFP 48-pin Assignment .................................................. 15

Figure 3.2-2 NuMicro Mini51 Series QFN 33-pin Assignment .................................................... 16

Figure 4.1-1 NuMicro Mini51 Series Block Diagram ................................................................... 21

Figure 5.3-1 NuMicro Mini51 Series Power Distribution Diagram............................................... 48

Figure 5.4-1 Clock Generator Block Diagram ................................................................................ 75

Figure 5.4-2 System Clock Block Diagram .................................................................................... 76

Figure 5.4-3 SysTick Clock Control Block Diagram ....................................................................... 76

Figure 5.4-4 AHB Clock Source for HCLK ..................................................................................... 77

Figure 5.4-5 Peripherals Clock Source Selection for PCLK........................................................... 78

Figure 5.4-6 Clock Source of Frequency Divider ........................................................................... 81

Figure 5.4-7 Block Diagram of Frequency Divider ......................................................................... 81

Figure 5.5-1 Analog Comparator Block Diagram ........................................................................... 99

Figure 5.5-2 Comparator Controller Interrupt Sources ................................................................ 100

Figure 5.5-3 Comparator Reference Voltage Block Diagram ...................................................... 101

Figure 5.6-1 ADC Controller Block Diagram ................................................................................ 108

Figure 5.6-2 ADC Clock Control................................................................................................... 109

Figure 5.6-3 A/D Conversion Result Monitor Logics Diagram ..................................................... 110

Figure 5.6-4 A/D Controller Interrupt ............................................................................................ 110

Figure 5.7-1 Flash Memory Control Block Diagram ..................................................................... 122

Figure 5.7-2 Flash Memory Organization..................................................................................... 124

Figure 5.7-3 Flash Memory Structure .......................................................................................... 126

Figure 5.7-4 ISP Procedure.......................................................................................................... 130

Figure 5.7-5 ISP Operation Flow.................................................................................................. 131

Figure 5.8-1 Push-Pull Output...................................................................................................... 143

Figure 5.8-2 Open-Drain Output .................................................................................................. 143

Figure 5.8-3 Quasi-bidirectional I/O Mode ................................................................................... 144

Figure 5.9-1 Bus Timing ............................................................................................................... 167

Figure 5.9-2 I2C Protocol .............................................................................................................. 168

Figure 5.9-3 Master Transmits Data to Slave .............................................................................. 168

Figure 5.9-4 Master Reads Data from Slave................................................................................ 169

Figure 5.9-5 START and STOP Condition ................................................................................... 169

Figure 5.9-6 Bit Transfer on the I2C Bus ...................................................................................... 170

Figure 5.9-7 Acknowledge on the I2C Bus ................................................................................... 171

Figure 5.9-8 I2C Data Shifting Direction ....................................................................................... 172

Feb 9, 2012

Page 6 of 342

Revision V1.03

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