MINI51 View Datasheet(PDF) - Unspecified

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MINI51

32-BIT MICROCONTROLLER - ARM Cortex™-M0

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NuMicro™ Mini51 Technical Reference Manual

Figure 5.9-9 I2C Time-out Count Block Diagram.......................................................................... 173

Figure 5.9-10 Legend for the Following Five Figures .................................................................. 185

Figure 5.9-11 Master Transmitter Mode....................................................................................... 186

Figure 5.9-12 Master Receiver Mode........................................................................................... 187

Figure 5.9-13 Slave Transmitter Mode......................................................................................... 188

Figure 5.9-14 Slave Receiver Mode............................................................................................. 189

Figure 5.9-15 GC Mode................................................................................................................ 190

Figure 5.10-1 Application Circuit Diagram ................................................................................... 192

Figure 5.10-2 PWM Block Diagram.............................................................................................. 193

Figure 5.10-3 PWM Generator 0 Architecture Diagram ............................................................... 193

Figure 5.10-4 PWM Generator 2 Architecture Diagram ............................................................... 194

Figure 5.10-5 PWM Generator 4 Architecture Diagram ............................................................... 194

Figure 5.10-6 Edge-aligned PWM................................................................................................ 196

Figure 5.10-7 PWM Edge-aligned Waveform Output .................................................................. 196

Figure 5.10-8 Edge-aligned Flow Diagram .................................................................................. 197

Figure 5.10-9 Legend of Internal Comparator Output of PWM-Timer ......................................... 198

Figure 5.10-10 PWM Timer Operation Timing ............................................................................. 198

Figure 5.10-11 Center-aligned Mode ........................................................................................... 199

Figure 5.10-12 PWM Center-aligned Waveform Output .............................................................. 200

Figure 5.10-13 Center-aligned Flow Diagram (INT_TYPE = 0) ................................................... 201

Figure 5.10-14 PWM Double Buffering Illustration....................................................................... 202

Figure 5.10-15 PWM Controller Output Duty Ratio...................................................................... 202

Figure 5.10-16 Dead-zone Insertion ............................................................................................ 203

Figure 5.10-17 Initial State and Polarity Control with Rising Edge Dead-zone Insertion............. 205

Figure 5.10-18 Motor Control PWM Architecture ......................................................................... 206

Figure 5.11-1 SPI Block Diagram................................................................................................. 228

Figure 5.11-3 SPI Slave Mode Application Block Diagram .......................................................... 229

Figure 5.11-4 Two Transfer (Burst Mode) in One Transaction .................................................... 231

Figure 5.11-5 Word Suspend Mode ............................................................................................. 231

Figure 5.11-6 Byte Reorder.......................................................................................................... 232

Figure 5.11-7 Byte Suspend Mode .............................................................................................. 232

Figure 5.11-8 Variable Serial Clock Frequency ........................................................................... 233

Figure 5.11-9 SPI Timing in Master Mode ................................................................................... 234

Figure 5.11-10 SPI Timing in Master Mode (Alternate Phase of SPICLK) .................................. 235

Figure 5.11-11 SPI Timing in Slave Mode ................................................................................... 235

Figure 5.11-12 SPI Timing in Slave Mode (Alternate Phase of SPICLK) .................................... 236

Feb 9, 2012

Page 7 of 342

Revision V1.03

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