AD9601BCPZ-250 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9601BCPZ-250

10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter

Analog Devices 

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AD9601

DA4 1

DA5 2

DA6 3

DA7 4

DA8 5

(MSB) DA9 6

DRVDD 7

DRGND 8

OVRA 9

NIC 10

NIC 11

(LSB) DB0 12

DB1 13

DB2 14

PIN 1

INDICATOR

AD9601

TOP VIEW

(Not to Scale)

PIN 0 (EXPOSED PADDLE) = AGND

42 AVDD

41 AVDD

40 CML

39 AVDD

38 AVDD

37 AVDD

36 VIN–

35 VIN+

34 AVDD

33 AVDD

32 AVDD

31 RBIAS

30 AVDD

29 PWDN

Figure 4. Pin Configuration

Table 7. Single Data Rate Mode Pin Function Descriptions

Pin No.

Mnemonic

Description

30, 32, 33, 34, 37, 38, 39, AVDD

41, 42, 43, 46

1.8 V Analog Supply.

7, 24, 47

DRVDD

1.8 V Digital Output Supply.

0

AGND1

Analog Ground.

8, 23, 48

DRGND1

Digital Output Ground.

35

VIN+

Analog Input—True.

36

VIN−

Analog Input—Complement.

40

CML

Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the

optimized internal bias voltage for VIN+/VIN−.

44

CLK+

Clock Input—True.

45

CLK−

Clock Input—Complement.

31

RBIAS

Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.)

Nominally 0.5 V.

28

RESET

CMOS-Compatible Chip Reset (Active Low).

25

SDIO/DCS

Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer

Select (External Pin Mode).

26

SCLK/DFS

Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).

27

CSB

Serial Port Chip Select (Active Low).

29

PWDN

Chip Power-Down.

49

DCO−

Data Clock Output—Complement.

50

DCO+

Data Clock Output—True.

53

DA0 (LSB)

Output Port A Output Bit 0 (LSB).

54

DA1

Output Port A Output Bit 1.

55

DA2

Output Port A Output Bit 2.

56

DA3

Output Port A Output Bit 3.

1

DA4

Output Port A Output Bit 4.

2

DA5

Output Port A Output Bit 5.

3

DA6

Output Port A Output Bit 6.

Rev. 0 | Page 9 of 32

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