CDB5342 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB5342 Datasheet PDF : 22 Pages
| |||
CS5342
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;
Logic "1" = VL, CL = 20 pF)
Parameter
MCLK Specifications
MCLK Period
MCLK Pulse Duty Cycle
Master Mode
SCLK falling to LRCK
SCLK falling to SDOUT valid
SCLK Duty Cycle
Slave Mode
Single Speed*
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Double Speed*
LRCK Duty Cycle
SCLK Period (Note 9)
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Quad Speed* (Note 2)
LRCK Duty Cycle
SCLK Period (Note 9)
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Symbol Min
tclkw
26
52
40
tmslr
-20
tsdo
-
Single-Speed
-
Double-Speed
-
Quad-Speed
-
Typ
Max
Unit
-
31
ns
-
1303
ns
-
60
%
-
20
ns
-
32
ns
50
-
%
50
-
%
33
-
%
40
-
tsclkw
290
-
45
-
tstp
10
-
thld
5
-
tslrd
-20
-
40
-
tsclkw
193
-
45
-
tstp
10
-
thld
5
-
tslrd
-20
-
40
-
tsclkw
104
-
40
-
tstp
10
-
thld
5
-
tslrd
-8
-
60
%
-
ns
55
%
-
ns
-
ns
20
ns
60
%
-
ns
55
%
-
ns
-
ns
20
ns
60
%
-
ns
50
%
-
ns
-
ns
8
ns
* For a description of Speed Modes, please refer to Table 1 on page 15
Notes: 9. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.
DS608PP2
11
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