IT8502 View Datasheet(PDF) - ITE Tech. INC.
Part Name
Description
Manufacturer
IT8502 Datasheet PDF : 398 Pages
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IT8502E/F/G
6.3.4 EC Interface Registers ..................................................................................................... 79
6.3.4.1 FBIU Configuration Register (FBCFG) ................................................................. 80
6.3.4.2 Flash Programming Configuration Register (FPCFG) ........................................... 80
6.3.4.3 Flash EC Code Banking Select Register (FECBSR)............................................. 81
6.3.4.4 Flash Memory Size Select Register (FMSSR) ...................................................... 82
6.3.4.5 Shared Memory EC Control and Status Register (SMECCS) ............................... 83
6.3.4.6 Shared Memory Host Semaphore Register (SMHSR) .......................................... 83
6.3.4.7 Flash Control 1 Register (FLHCTRL1R) ............................................................... 84
6.3.4.8 Flash Control 2 Register (FLHCTRL2R) ............................................................... 84
6.3.4.9 uC Control Register (UCCTRLR) ......................................................................... 84
6.3.4.10 Host Control 2 Register (HCTRL2R) .................................................................... 85
6.3.4.11 EC-Indirect Memory Address Register 0 (ECINDAR0) ......................................... 85
6.3.4.12 EC-Indirect Memory Address Register 1 (ECINDAR1) ......................................... 85
6.3.4.13 EC-Indirect Memory Address Register 2 (ECINDAR2) ......................................... 85
6.3.4.14 EC-Indirect Memory Address Register 3 (ECINDAR3) ......................................... 85
6.3.4.15 EC-Indirect Memory Data Register (ECINDDR).................................................... 85
6.3.4.16 Scratch SRAM 0 Address Low Byte Register (SCAR0L) ...................................... 86
6.3.4.17 Scratch SRAM 0 Address Middle Byte Register (SCAR0M).................................. 86
6.3.4.18 Scratch SRAM 0 Address High Byte Register (SCAR0H) ..................................... 86
6.3.4.19 Scratch SRAM 1 Address Low Byte Register (SCAR1L) ...................................... 86
6.3.4.20 Scratch SRAM 1 Address Middle Byte Register (SCAR1M).................................. 86
6.3.4.21 Scratch SRAM 1 Address High Byte Register (SCAR1H) ..................................... 86
6.3.4.22 Scratch SRAM 2 Address Low Byte Register (SCAR2L) ...................................... 86
6.3.4.23 Scratch SRAM 2 Address Middle Byte Register (SCAR2M).................................. 87
6.3.4.24 Scratch SRAM 2 Address High Byte Register (SCAR2H) ..................................... 87
6.3.4.25 Scratch SRAM 3 Address Low Byte Register (SCAR3L) ...................................... 87
6.3.4.26 Scratch SRAM 3 Address Middle Byte Register (SCAR3M).................................. 87
6.3.4.27 Scratch SRAM 3 Address High Byte Register (SCAR3H) ..................................... 87
6.3.4.28 Scratch SRAM 4 Address Low Byte Register (SCAR4L) ...................................... 87
6.3.4.29 Scratch SRAM 4 Address Middle Byte Register (SCAR4M).................................. 88
6.3.4.30 Scratch SRAM 4 Address High Byte Register (SCAR4H) ..................................... 88
6.3.4.31 Protect 0 Base Addr Register 0 (P0BA0R) ........................................................... 88
6.3.4.32 Protect 0 Base Addr Register 1 (P0BA1R) ........................................................... 88
6.3.4.33 Protect 0 Size Register (P0ZR) ............................................................................ 89
6.3.4.34 Protect 1 Base Addr Register 0 (P1BA0R) ........................................................... 89
6.3.4.35 Protect 1 Base Addr Register 1 (P1BA1R) ........................................................... 90
6.3.4.36 Protect 1 Size Register (P1ZR) ............................................................................ 90
6.3.4.37 Deferred SPI Instruction (DSINST)....................................................................... 90
6.3.4.38 Deferred SPI Address 15-12 (DSADR1)............................................................... 90
6.3.4.39 Deferred SPI Address 23-16 (DSADR2)............................................................... 90
6.3.4.40 Host Instruction Control 1 (HINSTC1) .................................................................. 91
6.3.4.41 Host Instruction Control 2 (HINSTC2) .................................................................. 91
6.3.4.42 Host RAM Window Control (HRAMWC) ............................................................... 92
6.3.4.43 Host RAM Winodw 0 Base Address [11:4] (HRAMW0BA[11:4]) ........................... 92
6.3.4.44 Host RAM Window 1 Base Address [11:4] (HRAMW1BA[11:4]) ........................... 92
6.3.4.45 Host RAM Window 0 Access Allow Size (HRAMW0AAS)..................................... 92
6.3.4.46 Host RAM Window 1 Access Allow Size (HRAMW1AAS)..................................... 93
6.3.5 Host Interface Registers................................................................................................... 93
6.3.5.1 Shared Memory Indirect Memory Address Register 0 (SMIMAR0)........................ 93
6.3.5.2 Shared Memory Indirect Memory Address Register 1 (SMIMAR1)........................ 93
6.3.5.3 Shared Memory Indirect Memory Address Register 2 (SMIMAR2)........................ 94
6.3.5.4 Shared Memory Indirect Memory Address Register 3 (SMIMAR3)........................ 94
6.3.5.5 Shared Memory Indirect Memory Data Register (SMIMDR).................................. 94
6.3.5.6 Shared Memory Host Semaphore Register (SMHSR) .......................................... 94
6.3.5.7 M-Bus Control Register (MBCTRL) ...................................................................... 94
6.4 System Wake-Up Control (SWUC) ............................................................................................... 95
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IT8502E/F/G V0.7.7
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