IT8502 View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

Manufacturer

IT8502

Embedded Controller

ITE Tech. INC. 

IT8502E/F/G

7.13.1 Overview ....................................................................................................................... 286

7.13.2 Features ........................................................................................................................ 286

7.13.3 Functional Description ................................................................................................... 286

7.13.4 EC Interface Registers ................................................................................................... 287

7.13.4.1 Indirect Host I/O Address Register (IHIOA) ........................................................ 287

7.13.4.2 Indirect Host Data Register (IHD)....................................................................... 287

7.13.4.3 Lock Super I/O Host Access Register (LSIOHA) ................................................ 287

7.13.4.4 Super I/O Access Lock Violation Register (SIOLV)............................................. 288

7.13.4.5 EC to I-Bus Modules Access Enable Register (IBMAE) ...................................... 288

7.13.4.6 I-Bus Control Register (IBCTL) .......................................................................... 288

7.13.5 EC2I Programming Guide .............................................................................................. 289

7.14 External Timer and External Watchdog (ETWD)......................................................................... 291

7.14.1 Overview ....................................................................................................................... 291

7.14.2 Features ........................................................................................................................ 291

7.14.3 Functional Description ................................................................................................... 292

7.14.3.1 External Timer Operation ................................................................................... 292

7.14.3.2 External WDT Operation.................................................................................... 293

7.14.4 EC Interface Registers ................................................................................................... 293

7.14.4.1 External Timer 1/WDT Configuration Register (ETWCFG) ................................. 294

7.14.4.2 External Timer 1 Prescaler Register (ET1PSR) .................................................. 294

7.14.4.3 External Timer 1 Counter High Byte (ET1CNTLHR) ........................................... 294

7.14.4.4 External Timer 1 Counter Low Byte (ET1CNTLLR) ............................................ 295

7.14.4.5 External Timer 2 Prescaler Register (ET2PSR) .................................................. 295

7.14.4.6 External Timer 2 Counter High Byte (ET2CNTLHR) ........................................... 295

7.14.4.7 External Timer 2 Counter Low Byte (ET2CNTLLR) ............................................ 295

7.14.4.8 External Timer 2 Counter High Byte 2 (ET2CNTLH2R) ...................................... 295

7.14.4.9 External Timer/WDT Control Register (ETWCTRL) ............................................ 296

7.14.4.10 External WDT Counter High Byte (EWDCNTLHR) ............................................. 296

7.14.4.11 External WDT Low Counter (EWDCNTLLR)....................................................... 296

7.14.4.12 External WDT Key Register (EWDKEYR) .......................................................... 296

7.15 General Control (GCTRL) .......................................................................................................... 298

7.15.1 Overview ....................................................................................................................... 298

7.15.2 Features ........................................................................................................................ 298

7.15.3 Functional Description ................................................................................................... 298

7.15.4 EC Interface Registers ................................................................................................... 298

7.15.4.1 Chip ID Byte 1 (ECHIPID1) ................................................................................ 299

7.15.4.2 Chip ID Byte 2 (ECHIPID2) ................................................................................ 299

7.15.4.3 Chip Version (ECHIPVER)................................................................................. 299

7.15.4.4 Identify Input Register (IDR)............................................................................... 299

7.15.4.5 Reset Status (RSTS) ......................................................................................... 300

7.15.4.6 Reset Control 1 (RSTC1) ................................................................................... 301

7.15.4.7 Reset Control 2 (RSTC2) ................................................................................... 301

7.15.4.8 Reset Control 3 (RSTC3) ................................................................................... 301

7.15.4.9 Reset Control 4 (RSTC4) ................................................................................... 302

7.15.4.10 Reset Control DMM (RSTDMMC) ...................................................................... 302

7.15.4.11 Base Address Select (BADRSEL) ...................................................................... 302

7.15.4.12 Wait Next Clock Rising (WNCKR) ...................................................................... 302

7.15.4.13 Oscillator Control Register (OSCTRL)................................................................ 303

7.15.4.14 Special Control 1 (SPCTRL1) ............................................................................ 303

7.15.4.15 Reset Control Host Side (RSTCH) ..................................................................... 303

7.15.4.16 Generate IRQ (GENIRQ) ................................................................................... 304

7.16 External GPIO Controller (EGPC) .............................................................................................. 305

7.16.1 Overview ....................................................................................................................... 305

7.16.2 Features ........................................................................................................................ 305

7.16.3 Functional Description ................................................................................................... 305

7.16.4 EC Interface Registers ................................................................................................... 305

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IT8502E/F/G V0.7.7

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