IT8502F View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

Manufacturer

IT8502F

Embedded Controller

ITE Tech. INC. 

Contents

Table 5-14. Pin Descriptions of GPIO Interface ............................................................................................ 22

Table 5-15. Pin Descriptions of Hardware Strap........................................................................................... 23

Table 5-16. Pin Descriptions of ADC Input Interface..................................................................................... 23

Table 5-17. Pin Descriptions of DAC Output Interface .................................................................................. 23

Table 5-18. Pin Descriptions of Clock .......................................................................................................... 23

Table 5-19. Pin Descriptions of Power/Ground Signals ................................................................................ 23

Table 5-20. Power States ............................................................................................................................ 25

Table 5-21. Pin States of LPC Bus Interface ................................................................................................ 27

Table 5-22. Pin States of Keyboard Matrix Scan Interface............................................................................ 27

Table 5-23. Pin States of SMBus Interface................................................................................................... 27

Table 5-24. Pin States of PS/2 Interface ...................................................................................................... 27

Table 5-25. Pin States of PWM Interface ..................................................................................................... 27

Table 5-26. Pin States of Wake Up Control Interface ................................................................................... 28

Table 5-27. Pin States of UART Interface .................................................................................................... 28

Table 5-28. Pin States of EGPC Interface .................................................................................................... 28

Table 5-29. Pin States of SSPI Interface ...................................................................................................... 28

Table 5-30. Pin States of Serial Port Interface.............................................................................................. 28

Table 5-31. Pin States of GPIO Interface ..................................................................................................... 28

Table 5-32. Pin States of ADC Input Interface.............................................................................................. 29

Table 5-33. Pin States of DAC Output Interface ........................................................................................... 29

Table 5-34. Pin States of Clock.................................................................................................................... 29

Table 5-35. Reset Sources .......................................................................................................................... 31

Table 5-36. Reset Types and Applied Module .............................................................................................. 31

Table 5-37. Clock Types .............................................................................................................................. 32

Table 5-38. Power Saving by EC Clock Operation Mode.............................................................................. 34

Table 5-39. Module Status in Each Power State/Clock Operation................................................................. 35

Table 5-40. Pins with Pull Function .............................................................................................................. 36

Table 5-41. Pins with Schmitt-Trigger Function ............................................................................................ 36

Table 5-42. Signals with Open-Drain Function ............................................................................................. 36

Table 6-1. LPC/FWH Response................................................................................................................... 39

Table 6-2. Host View Register Map, PNPCFG ............................................................................................. 42

Table 6-3. Host View Register Map, Logical Devices ................................................................................... 42

Table 6-4. Host View Register Map via Index-Data I/O Pair, Standard Plug and Play Configuration Registers43

Table 6-5. Interrupt Request (IRQ) Number Assignment, Logical Device IRQ via SERIRQ ........................... 43

Table 6-6. Logical Device Number (LDN) Assignments ................................................................................ 44

Table 6-7. Host View Register Map via Index-Data I/O Pair, UART1 Logical Device..................................... 49

Table 6-8. Host View Register Map via Index-Data I/O Pair, SWUC Logical Device...................................... 51

Table 6-9. Host View Register Map via Index-Data I/O Pair, KBC / Mouse Interface Logical Device ............. 53

Table 6-10. Host View Register Map via Index-Data I/O Pair, KBC / Keyboard Interface Logical Device ....... 55

Table 6-11. Host View Register Map via Index-Data I/O Pair, SMFI Interface Logical Device ....................... 57

Table 6-12. Host View Register Map via Index-Data I/O Pair, BRAM Logical Device .................................... 59

Table 6-13. Host View Register Map via Index-Data I/O, PMC1 Logical Device............................................ 61

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IT8502E/F/G V0.7.7

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