IT8502E View Datasheet(PDF) - ITE Tech. INC.
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Description
Manufacturer
IT8502E Datasheet PDF : 398 Pages
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Revision History
Section
5, 7
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Revision History
Revision
Table 5-5. Pin Descriptions of SMBus Interface
7.7.4 EC Interface Registers231
Added one SMBus master.
Table 5-3. Pin Descriptions of Serial Peripheral Interface (SSPI)
Added SBUSY pin.
Table 5-12.
Newly added table.
Table 5-18. Pin Descriptions of Clock
Added CK32KOUT.
Table 6-6. Logical Device Number (LDN) Assignments
6.2.12 Power Management I/F Channel 3 Configuration Registers
6.6.5 EC Interface Registers
Added PMC3.
6.2.13.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
6.3.3.17 Host Side to EC Scratch RAM (H2RAM)
6.2.8.9HLPC RAM Base Address [15:12] (HLPCRAMBA[15:12])
6.2.8.10HLPC RAM Base Address [23:16] (HLPCRAMBA[23:16])
6.3.4.42 Host RAM Window Control (HRAMWC)
6.3.4.43 Host RAM Winodw 0 Base Address [11:4] (HRAMW0BA[11:4])
6.3.4.44 Host RAM Window 1 Base Address [11:4] (HRAMW1BA[11:4])
6.3.4.45 Host RAM Window 0 Access Allow Size (HRAMW0AAS)
6.3.4.46 Host RAM Window 1 Access Allow Size (HRAMW1AAS)
Added H2RAM function.
Errata:
6.3.4.5Shared Memory EC Control and Status Register (SMECCS)
Bit 4-3 were revised.
6.3.4.7 Flash Control 1 Register (FLHCTRL1R)
Support “Fast Read Dual Output” and “Fast Read Dual Input/Output”
6.3.4.40 Host Instruction Control 1 (HINSTC1)
Added SCECB bit.
6.6.5.10 Mailbox Control (MBXCTRL)
Added DINT bit.
7.2.4 EC Interface Registers
New INTC channel INT64-79 added.
7.3.4 EC Interface Registers
New WUC channel WUI24-31 added.
7.4.4 EC Interface Registers
KSI/KSO used as GPIO.
7.5.3.2 General Control 1 Register (GCR1)
Added bit 6.
7.5.3.3 General Control 2 Register (GCR2)
Added bit 6-4.
7.5.3.4 General Control 3 Register (GCR3)
7.5.3.5 General Control 4 Register (GCR4)
Newly added registers.
7.7.3.1 SMBus Master Interface
Modification for I2C compatible.
7.7.3.5 Description of SMCLK and SMDAT Line Control in Software Mode
Newly added description.
Page No.
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IT8502E/F/G V0.7.7
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