IT8502 View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

Manufacturer

IT8502

Embedded Controller

ITE Tech. INC. 

Contents

CONTENTS

1. Features 1

2. General Description.................................................................................................................................. 3

3. System Block Diagram ............................................................................................................................. 4

3.1 Block Diagram ............................................................................................................................... 4

3.2 Host/EC Mapped Memory Space ................................................................................................... 5

3.3 EC Mapped Memory Space ........................................................................................................... 8

3.4 Register Abbreviation..................................................................................................................... 9

4. Pin Configuration.................................................................................................................................... 11

4.1 Top View ..................................................................................................................................... 11

5. Pin Descriptions ..................................................................................................................................... 19

5.1 Pin Descriptions ........................................................................................................................... 19

5.2 Chip Power Planes and Power States .......................................................................................... 25

5.3 Pin Power Planes and States ....................................................................................................... 26

5.4 PWRFAIL# Interrupt to INTC....................................................................................................... 30

5.5 Reset Sources and Types ............................................................................................................ 31

5.5.1 Related Interrupts to INTC ............................................................................................... 31

5.6 Chip Power Mode and Clock Domain ........................................................................................... 32

5.7 Pins with Pull, Schmitt-Trigger or Open-Drain Function ................................................................ 36

5.8 Power Consumption Consideration .............................................................................................. 37

6. Host Domain Functions .......................................................................................................................... 39

6.1 Low Pin Count Interface ............................................................................................................... 39

6.1.1 Overview ......................................................................................................................... 39

6.1.2 Features .......................................................................................................................... 39

6.1.3 Accepted LPC Cycle Type ............................................................................................... 39

6.1.4 Debug Port Function ........................................................................................................ 40

6.1.5 Serialized IRQ (SERIRQ)................................................................................................. 40

6.1.6 Related Interrupts to WUC ............................................................................................... 40

6.1.7 LPCPD# and CLKRUN# .................................................................................................. 40

6.1.8 Check Items..................................................................................................................... 40

6.2 Plug and Play Configuration (PNPCFG) ....................................................................................... 42

6.2.1 Logical Device Assignment .............................................................................................. 44

6.2.2 Super I/O Configuration Registers.................................................................................... 45

6.2.2.1 Logical Device Number (LDN).............................................................................. 45

6.2.2.2 Chip ID Byte 1 (CHIPID1) .................................................................................... 45

6.2.2.3 Chip ID Byte 2 (CHIPID2) .................................................................................... 45

6.2.2.4 Chip Version (CHIPVER) ..................................................................................... 45

6.2.2.5 Super I/O Control Register (SIOCTRL) ................................................................ 45

6.2.2.6 Super I/O IRQ Configuration Register (SIOIRQ)................................................... 46

6.2.2.7 Super I/O General Purpose Register (SIOGP) ..................................................... 46

6.2.2.8 Super I/O Power Mode Register (SIOPWR) ......................................................... 46

6.2.3 Standard Logical Device Configuration Registers ............................................................. 46

6.2.3.1 Logical Device Activate Register (LDA)................................................................ 47

6.2.3.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 47

6.2.3.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 47

6.2.3.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 47

6.2.3.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 47

6.2.3.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 47

6.2.3.7 Interrupt Request Type Select (IRQTP)................................................................ 48

6.2.3.8 DMA Channel Select 0 (DMAS0) ......................................................................... 48

6.2.3.9 DMA Channel Select 1 (DMAS1) ......................................................................... 48

6.2.4 Serial Port 1 (UART1) Configuration Registers................................................................. 49

6.2.4.1 Logical Device Activate Register (LDA)................................................................ 49

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IT8502E/F/G V0.7.7

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