IT8502E View Datasheet(PDF) - ITE Tech. INC.
Part Name
Description
Manufacturer
IT8502E Datasheet PDF : 398 Pages
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IT8502E/F/G
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 49
6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 49
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 49
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 49
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 50
6.2.4.7 Interrupt Request Type Select (IRQTP)................................................................ 50
6.2.4.8 High Speed Baud Rate Select (HHS) ................................................................... 50
6.2.5 System Wake-Up Control (SWUC) Configuration Registers ............................................. 51
6.2.5.1 Logical Device Activate Register (LDA)................................................................ 51
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 51
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 51
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 51
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 51
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 51
6.2.5.7 Interrupt Request Type Select (IRQTP)................................................................ 52
6.2.6 KBC / Mouse Interface Configuration Registers................................................................ 53
6.2.6.1 Logical Device Activate Register (LDA)................................................................ 53
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 53
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 53
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 53
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 53
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 54
6.2.6.7 Interrupt Request Type Select (IRQTP)................................................................ 54
6.2.7 KBC / Keyboard Interface Configuration Registers ........................................................... 55
6.2.7.1 Logical Device Activate Register (LDA)................................................................ 55
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 55
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 55
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 55
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 55
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 55
6.2.7.7 Interrupt Request Type Select (IRQTP)................................................................ 56
6.2.8 Shared Memory/Flash Interface (SMFI) Configuration Registers ...................................... 57
6.2.8.1 Logical Device Activate Register (LDA)................................................................ 57
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 57
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 57
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 57
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 58
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 58
6.2.8.7 Interrupt Request Type Select (IRQTP)................................................................ 58
6.2.8.8 Shared Memory Configuration Register (SHMC) .................................................. 58
6.2.8.9 HLPC RAM Base Address [15:12] (HLPCRAMBA[15:12]) .................................... 58
6.2.8.10 HLPC RAM Base Address [23:16] (HLPCRAMBA[23:16]) .................................... 58
6.2.9 BRAM Configuration Registers......................................................................................... 59
6.2.9.1 Logical Device Activate Register (LDA)................................................................ 59
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 59
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 59
6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 59
6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 59
6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 60
6.2.9.7 Interrupt Request Type Select (IRQTP)................................................................ 60
6.2.9.8 P80L Begin Index (P80LB)................................................................................... 60
6.2.9.9 P80L End Index (P80LE) ..................................................................................... 60
6.2.9.10 P80L Current Index (P80LC)................................................................................ 60
6.2.10 Power Management I/F Channel 1 Configuration Registers.............................................. 61
6.2.10.1 Logical Device Activate Register (LDA)................................................................ 61
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 61
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IT8502E/F/G V0.7.7
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